Hi, I’m
Santhosh S
Bangalore
Summary
Strategic Senior Staff Engineer with over 14 years of expertise in the VLSI lifecycle, specializing in Power Integrity (EMIR) Signoff and Power Optimization for high-performance CPU, GPU, and SoC designs. Proven track record at MediaTek in leading silicon success across advanced nodes from 28nm down to 2nm. Good in bridging the gap between library development (SRAM/Standard Cells) and full-chip closure to ensure long-term reliability and PPA excellence. Adept at methodology innovation, cross-functional crisis management.
Overview
14
years of professional experience
Work History
MediaTek Bangalore Pvt. Ltd.
Senior staff Engineer
07.2023 - Current
Job overview
- Cross-functional Leadership and crisis Management: Directed late-stage tapeout EMIR closure by resolving critical dynamic IR drop violations; collaborated with packaging teams to analyze bump-wise Resistance/Inductance and utilized IR-aware STA to prove safety margins, preventing scheduled delays.
- Methodology and shift left optimization: designed and implemented an “Early Health Check” methodology to identify missing vias and power grid weakness, resistance check and bump coverage analysis prior to SpefOut stage, significantly reducing; late-stage ECO cycles and accelerating overall tapeout TAT.
- Stakeholder Negotiation and timing closure: navigated complex flow corrections (Voltus input read errors) during SpefOut stages implementing input checks, collaborating with STA teams to extract critical net lists; developed PG reinforcement plan (clock cells, hotspots, global fill) that fixed IR violations with zero impact to timing closure and Physical verification.
- Team Development and Mentorship: Mentored juniors and mid-level engineers in advanced EMIR debugging methodologies and cross-functional communication, elevating the team’s ability to independently resolve dynamic IR root causes.
- GPU Power signoff: Generate functional vectors for IR team and deliver the PTPX (primepower) powers to PD, PI team.
- GPU DFT IR pattern generation ownership: Deliver test mode patterns (Scan capture and OCC) for IR signoff.
MediaTek Bangalore Pvt. Ltd.
Staff Engineer
07.2019 - 06.2023
Job overview
- Collaborated with cross teams to develop and implement “Early IR Health checks” like Grid resistance check for instances, bump coverage, early scanIR check etc.
- Automated the IR signoff flow for easy Dashboard view of IR results summary and instances IR drop/Resistance histogram analysis.
- Planned bumpout and suggested SRAM and ESD cell placements in floorplan.
- Implemented multiple PG grid designs for ARM CPU’s PPA optimization and evaluated each PG and selected which is best for timing and IR.
- Involved in execution and analysis of E2E IR signoff activities like bump planning, RDL design, Static IR, dynamic IR (Vector and vector less), scan capture and OCC IR closure, CPM models generation for each mode.
- Automated FSDB data extraction and plot the activity histogram using the Verdi Python NPI modules for early analysis.
- Involved in the evaluation of custom macro designs for CPU/GPU design to improve the area and performance.
MediaTek Bangalore Pvt. Ltd.
Senior Engineer
07.2015 - 06.2019
Job overview
- Worked on the standard cells characterization and Quality analysis.
- Automated the StdCells QA flow and implemented many QA checks to verify the different views of stdcells library like gds/lef/milkyway/ndm/apl/pgv/ces/ndlm/spice etc.
- Automated the library benchmark flow using Genus synthesis tool.
- Worked on the IR signoff execution of ARM CPU design.
Immensa semiconductor Pvt. Ltd.
Design Engineer
08.2014 - 06.2015
Job overview
- SRAM verification flow: Worked on Automated Verilog and spice testbench generation.
- Worked as a contractor in ARM company on StdCells characterization.
LSI India R&D Pvt. Ltd.
Project Trainee
08.2012 - 07.2014
Job overview
- Involved in SRAM compilers verification flow called Pattern Generation.
- Developed the GUI for the SRAM verification flow for ease of operation.
Education
Bapuji Institute of Engineering and Technology (VTU)
B.E. from Electronics & Communication
01-2012
University Overview
GPA: 79.67%
Skills
EMIR signoff and methodologies
Power Grid designs (PDN)
Power Signoff (PTPX)
Know coding in TCL, Python, Perl, Shell, R
EDA tools knowledge: Voltus, Redhawk, Fusion compiler, Innovus, Genus, PrimeTime, PrimePower
Timeline
Senior staff Engineer
MediaTek Bangalore Pvt. Ltd.
07.2023 - Current
Staff Engineer
MediaTek Bangalore Pvt. Ltd.
07.2019 - 06.2023
Senior Engineer
MediaTek Bangalore Pvt. Ltd.
07.2015 - 06.2019
Design Engineer
Immensa semiconductor Pvt. Ltd.
08.2014 - 06.2015
Project Trainee
LSI India R&D Pvt. Ltd.
08.2012 - 07.2014
Bapuji Institute of Engineering and Technology (VTU)
B.E. from Electronics & Communication