Seemant Raj Chourey

As an experienced Design Verification Engineer, I have a proven track record in the semiconductors industry. My expertise includes advanced verification methodologies such as UVM and Vplatform, utilizing System Verilog and C++ languages. Additionally, I m m proficient in scripting with Perl, Python, bash, and Makefiles. I hold a PG-Diploma in VLSI and a B.Tech in Electronics and Communications.

• Design Verification Engineer, ONSEMI, 09/01/20 to 08/31/21, Working as a Design Verification Engineer and Writing golden reference models for image sensor for Module level(C++) and Top level(Perl)., UVM, System Verilog, C++, Perl, SVN
• Functional C++ and Python Simulator, ACL Digital, 09/01/21 to currently working, Working with architecture team of a functional C++ and Python Simulator (Imperas and Specsim) of RISCV processor., C++, Python, Perl, GIT, FORK, VM Box
• Functional/Performance C++ Software Simulator, US technologies, 11/01/18 to 08/31/20, Part of design and modelling team of a functional/performance C++ software simulator of Intel GPU architectures., C++, Ruby, Python, Unix Shell Scripting, Git, Perforce, SVN, Jira
• Windows Automation Team, US technologies, Working as a Developer and Execution engineer., Python, Windows, BIOS, Relay, Platforms, Automation
• Validation Engineer, US technologies, Working as a Validation engineer in executing tests and bringing up functional Bugs in RTL.
• Verification of Sub-Systems with Standard Communication Interface AHB, RV-VLSI Design Center, Project work involves verification of SPI, UART and I2C., Mentor Graphics Questa-Sim