Shanmukha Venkatesh Bhat

Microchip Technology Inc.

07.2024 - Current

Configured and executed Insight ERC flows for Power Connection and Hot N-Well scans across analog macros, enabling early detection of electrical rule violations and systematic waiver generation for false errors.
Set up and ran Calibre PERC tool on analog macros to identify Electrostatic Discharge (ESD), Electrical Overstress (EOS), and cross-power-domain signal violations; analyzed results and generated waivers for false positives.
Developed macro-specific testbenches and executed CheckDC Path and CheckZNode analyses using Synopsys FineSim Pro to validate analog macros for potential connectivity and floating node issues.
Set up and executed testbenches in Cadence Virtuoso to verify the functionality of a high-speed comparator macro across all Process, Voltage, and Temperature (PVT) corners, ensuring compliance with Design Objective Specifications (DOS)
Gained hands-on experience with Cadence Liberate to generate NLDM-based .lib files for various analog macros; understood the process of characterizing timing and power information used in Liberty format.
Analyzed the leakage power characterization process in Cadence Liberate by extracting and re-simulating the generated testbench setup in Cadence Virtuoso to cross-verify leakage power values reported in the Liberty (.lib) file.

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