SHASHIKIRAN R

Overall 5+ Years of hands-on experience in VLSI domain, executing from netlist to GDSII using EDA tools and worked for clients like AMD, MEDIATEK and INDIE SEMICONDUCTOR on lower technology nodes. 1 Year and 11 months of work experience in AMD through Whizchip Design Technologies. 1 Year and 4 months of work experience in MEDIATEK through Insemi Technologies. 2 Year and 6 months of wok experience in Cadence Design Systems (INVECAS).

• Mother's Name: Gayathri R
• Date of Birth: 04/27/1993
• Nationality: Indian
• Marital Status: Single

• Newsprint
• Playing Cricket
• Badminton
• Cycling

• ICC2 Block Level Implementation training from Synopsys Inc.
• Physical Design training from VLSIGURU TRAINING INSTITUTE, Bangalore using Synopsys IC Compiler.
• Cadence INNOVUS block level Implementation Certification.