SHRAY TYAGI

I am a skilled Design Engineer with over 3 years of experience in timing closure and working with EDA tools like Prime Time, ICC2 and Fusion Comple Understanding static timing analysis understanding of physical design flows, synthesis processes. I've actively contributed to projects for reputable clients such as Intel and AMD. I am dedicated to achieving optimal design performance and resolving complex engineering challenges

A.) CNIC (Intel 18A/1.8 nm),

Tool: Fusion Compiler, Star Primetime.

Successfully implemented a complex digital block from RTL to GDS-IL meeting aggressive timing and power targets and ensuring all the sign-off checks are met.

Performed in-depth floor planning and power planning with its new backside metal to meet all health checks for design.

Achieved timing closure at all corners by implementing efficient placement, balancing clock trees to minimize skew, and performing comprehensive timing ECO.

B.) Nova Lake (Intel 7nm):

Project focused on advanced timing closure techniques for a client in the semiconductor industry.

Performed full-chip timing closure of interface paths and intra paths setup and hold. Fixed techniques of the assigned blocks and generated Manual ECOs during ECD stage.

Debugged UCR and constraint related issues, and modified clock.

C.) Strix 1 (AMD 7nm), Involved in the design project for a major client, focusing on sanity checks and worst-case scenarios. Initial net-list checks and SDC sanity checks.

Performed macro placement after studying module connectivity and debugged unconstrained endpoints.

D.) Volcano (28nm):

Optimized design for performance in terms of timing, area and power.

9 Metal layers were used in design.

Placed macros in the design according to the guidelines.

Placed physical cells like wellsap and endcap cells were added.

Placement of St Cells in the design.

Design operated at 4 frequency.

Total macros in design: 40 and total cell count: 54K.

Analyzed QR and debugged high logic level issues.