Siddhi Karadkhedkar
Bangalore
Summary
Results-driven Design Verification Engineer with 7 years in semiconductor industry, expertly reducing simulation time and enhancing chip quality employing SystemVerilog and UVM tools.
Overview
2027
2027
years of professional experience
Work History
Staff Engineer
SanDisk
03.2023 - Current
- Led pillar in logic module block for 100% closure and debug
- Worked on bring-up of a complex formal MTB from scratch for early bug detection as part of previous lessons learnt. (Awarded trade secret for the innovative approach)
- Worked on development, debug and closure of assertions related to logic block design updates for the next generation memory chip architecture.
Staff Engineer
Western Digital
3 2021 - 02.2023
- Worked on compact form factor current measurement pcb with 5msps speed with high accuracy (equal to 5GHz scope) to work in chamber from -40C to 120C
- Worked on communication protocols like SPI, I2C, UART, PCIe for tester hardware development
- Worked on multiple innovation ideas that helped in CAPEX saving. One of the ideas was granted as patent and is pending for approval from US govt. (US20250246837A1)
Sr. Engineer
Western Digital
08.2019 - 03.2022
- Pioneered lab setup for hardware team along with equipment procurement and opex planning.
- Worked on ESD compliance, precision soldering under microscope
- Worked on evaluation kits for comparing high speed precision ADC for current measurement
Education
Master of Science - Microelectronics
BITS, Pilani Goa Campus
Goa06-2019
Bachelor of Science - Electronics Engineer
VIT, Pune
Pune05-2016
Skills
- SystemVerilog
- UVM Methodologies
- RTL Design
- FPGA Prototyping
- Functional Coverage
- Jasper Gold
- VLSI Design
- Python Scripting
Timeline
Staff Engineer
SanDisk
03.2023 - Current
Sr. Engineer
Western Digital
08.2019 - 03.2022
Staff Engineer
Western Digital
3 2021 - 02.2023
Master of Science - Microelectronics
BITS, Pilani Goa Campus
Bachelor of Science - Electronics Engineer
VIT, Pune