Soumya Rai
Bengaluru
Summary
Dynamic R&D Staff Engineer at Synopsys with expertise in SystemVerilog and UVM, specializing in DDR5 protocol verification. Proven track record in developing robust test benches and achieving comprehensive functional coverage. Strong analytical skills complemented by effective collaboration within cross-functional teams to drive project success.
Overview
9
9
years of professional experience
1
1
Certification
Work History
R&D Staff Engineer
Synopsys
05.2025 - Current
- Collaborated with the VIP team focusing on DDR5 protocol.
- Designed and implemented self-checking test benches using UVM and System Verilog.
- Developed verification components including monitors and behavioral models.
- Implemented checkers for self-refresh mode of DRAM and validated them with system test benches.
- Built IP verification test plans, testbenches, and environments using System Verilog and UVM.
- Maintained regression tests for regular test cycles.
- Developed functional coverage for MRDIMM and CSODIMM.
- Integrated support for 9600 speed bins in DRAM.
Design and Verification Engineer
Cadence Design Systems
08.2022 - 05.2025
- Responsible for IP verification and quality engineering for Cadence Xcelium.
- Developed and executed test plans for Xcelium features.
- Built IP verification test plans, testbenches, and environments using System Verilog and UVM.
- Maintained regression tests for regular test cycles.
- Worked on cross-technologies like Xmclone, MSIE, and XFORM.
Digital Design Engineer
Signoff Semiconductors Pvt. Ltd.
07.2021 - 08.2022
- Developed UVM functional validation tests in SystemVerilog for IP and SoC level verification.
- Verified IPs including I2C, UART, SPI, AXI, APB, and AHB VIPs as agents in testbench environments.
- Created modular verification collateral including monitors, scoreboards, and checkers.
- Analyzed coverage gaps and maintained comprehensive verification test plans.
Design and Verification Intern
Sion Semiconductors
11.2020 - 06.2021
- Worked on RTL coding, design, and verification of digital designs including Asynchronous FIFO, FSM-based designs, Single/Dual Port RAM, and ALU.
Quantitative Aptitude Trainer
Ashoka Institute of Technology and Management
10.2017 - 05.2019
Programmer Analyst Trainee
Cognizant Technology Solutions
12.2016 - 06.2017
- Worked as a C#.NET Developer.
Education
M.Tech - Electronics and Communication Engineering
Dr. A.P.J. Abdul Kalam Technical University
Lucknow01.2021
B.Tech - Electronics and Communication Engineering
Galgotias University
Greater Noida01.2016
Skills
- Verilog
- SystemVerilog
- VHDL
- Python
- Shell scripting
- C#
- UVM
- RTL coding
- Coverage
- DDR5
- IP verification
- AHB
- APB
- AXI
- SPI
- I2C
- UART
- Synopsys VCS
- Cadence Xcelium
- Mentor QuestaSim
- Xilinx Vivado
- Linux
- Functional coverage
- Digital design
Certification
- Verilog HDL: VLSI Hardware Design Comprehensive Masterclass
- Python 101
Timeline
R&D Staff Engineer
Synopsys
05.2025 - Current
Design and Verification Engineer
Cadence Design Systems
08.2022 - 05.2025
Digital Design Engineer
Signoff Semiconductors Pvt. Ltd.
07.2021 - 08.2022
Design and Verification Intern
Sion Semiconductors
11.2020 - 06.2021
Quantitative Aptitude Trainer
Ashoka Institute of Technology and Management
10.2017 - 05.2019
Programmer Analyst Trainee
Cognizant Technology Solutions
12.2016 - 06.2017
M.Tech - Electronics and Communication Engineering
Dr. A.P.J. Abdul Kalam Technical University
B.Tech - Electronics and Communication Engineering
Galgotias University
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