Silpa M S

Project 1 : CCL (Chip to Chip Link) for XT and KX

Chip-to-Chip Link is used for connecting multiple chips either within same ASIC package or ASICs on different line cards in a fabric based system.

· Ownership of BIST , Frame header error insertion , Loop back and legacy compatibility verification.

· Developed test case in using system verilog language in UVM environment

. Developed test cases for BIST with different functionalities, including reconfiguring, error injection, and loopback.

. Verified new features and worked on coverage closure.

. Cross chip verification also completed using the same TB environment.

. Regression debugging and test fixing.

Project 1 : PCIe IDE (Integrity and Data Encryption) security

Integrity and Data Encryption(IDE) provides confidentiality, integrity, and replay protection for TLPs.This ECN defines in-line security at the Transaction Layer, providing a consistent toolset fro estgablishing security over PCIe data in transit.

· Spec analysis, feature extraction and test development

· Developed test cases using sytemverilog language.

· Implemented test cases with UVM call back

· Regression debug and test fix

Project 1 : PCIe Gen 2 Phy Layer RX verification

· Spec analysis and feature extraction

· Test plan creation and test development

· Regression debug and test fix

Project 2 : AHB VIP development

· Spec analysis and feature extraction

· UVC development

· Regression debug and test fix