SK ABDUL FAHEMID

Role: Responsibilities: -Senior Verification

• TJA1104(McLena) is 100 BASE-T1 Automotive Ethernet PHY.
• Mclena is intended for system that need external 100 Base -T1 PHY.
• The product is build around Si-proven butterfly which is 100Base -T1 transceiver IP with Additional interface to support SGMII/xMII PHY Interface.
• Implantation of GLS from scratch.
• Debugging and fixed some failing tests.
• Perform Unit delay and timing delay gate level simulation for all required test case with provided SDF’s for SMGII, XMII and no- VIP IP’s
• Debugged Flop initialization issues and X propagation.

Role & Responsibility: - WHS_HALK (server chip)-s3m Interface client: -Intel

• Understanding s3m bring up in WHS arc-based C test Development.
• Implementation for SMBUS test case and debugging.
• Implantation for SPI Flash test case
• Implement a checker for SPI flash.
• GLS implementation.
• Intel – x-propagation excluding incomplete test point and debug test case.
• I2C Debugging a Test Case.
• Generating are list passed and fail using regression using python automation.

Role & Responsibility: -Ethernet-800G client: -Cyient

• Automatic FEC/CRC generation and monitoring/checking.
• Managed and inspected instruments and equipment for manufacturing.
• Test case generation and checking (Directed, random and semi-random/constrained-random test cases) .
• 100G lane round robin is followed on byte basis.
• Round Robin scheme on packet basis for 800G traffic.
• Integration &Testing, Fixing the bug and updating.
• Implementation test case for scoreboard.

Role & Responsibility: - Uart

Ø Understanding the specification and architecture.

Ø Understanding the architecture and developing test scenarios according to the verification plan.

Ø To Build the test bench and writing the sequences.

Ø Write the coverage for TX, UART Interrupt coverage, and interface coverage.

Ø Verify the shift registers and baud rate generator to Rx.

Ø To validate the bugs for single regression and multi-regression

Ø Raising the BUGS for corner cases and support the RTL team to understand the issues and then validate the fixes.

Role & Responsibility: - Ebonics / DO-254-777x client:-Boeing

• Development a scoreboard and Arbiter.
• Triggering Error or Fatal Error NVM through VIP modification.
• Implantation test case
• Predictor and sequences development as per requirement.
• Develop Verification Test Case by reviewing requirement provided by client and file Problem Report on requirement at initial level if any conflicts found.
• Verification of VHDL Design of client propriety interfaces used in design of PLDs.
• Worked on Code Coverage and modify the procedure to achieve required percentage of coverage.
• Review the Results of the Test and file the Problem Report for any conflicts found.
• Test Plan creation and finding a link Error updating.

Role & Responsibility: - DDR-3 client: - cadences

• Developing test bench. Understanding the architecture and developing test scenarios according to the verification plan.
• To build the for driver, sequences.
• Functional coverage analyses through the coverage report make a 100 %.
• Exacting Test Plan Creation.
• Validation process after completing the verification.

Role & Responsibility: - Analog Discovery with hip board client: - cadences

• Developing test bench. Understanding the architecture and developing test scenarios according to the verification plan.
• To build the tb for driver, sequencer and monitor, sequences
• The Analog Discovery and the hip board create a 3 test through wave from Air pump, water pump, and led.
• Functional coverage analyze through the coverage report make a 100 %.
• The start digital discovery executing the project capturing the wave from different cycle time.
• Monitor debugs using developed test cases and report AHI report with wave from automated Generate.

Role & Responsibility: -Router-SG300-52p-28 ports client: - Cisco

• Understanding the architecture and developing test scenarios according to the verification plan.
• Write a Verification Environment generate a signal and stimulate through DUT.
• The consists of 3 different fields Header, data, FCS.
• DUT under the test Verification IP to a Signals and environment through the coverage.
• The simulation time Bed FCS and Good FCS Report Showing.
• The overall design, preparing a verification plan, creates test-benches, debug verification results.

Role & Responsibility: -Wireless Monitor and receiver. client:- Honeywell

• As per the Requirement, preparing a verification plan, creates test-benches,
• Understanding the architecture and developing test case scenarios according to the Blocks
• Analyze a code coverage and create a “init file” write a exclusion for 100 % coverage.
• To Build the test bench and writing the sequences.
• Implement a coverage and predictor as per a requirement.
• Designed and analyzed test bench environment and perform required modifications.
• Experience in system level and module / block level verification ARM based SOC.

Role & Responsibility: -DDR-3 client: - Feature Electronic

• As per the client Requirement or Specification implement a design
• Synthesis tools can detect RAM designs in the HDL code.
• The design unit dynamically switches between read and writes operations.
• Filling and fixing the verification bugs.
• Debugged and trace back issues using Sim-Vision tool.
• Assigned to create test cases to verify the BUS and Interrupts.

Role & Responsibility: -USB-3.0 client: - True Chip

• As per the client Requirement or Specification implement a design
• Synthesis tools can detect RAM designs in the HDL code.
• The design unit dynamically switches between read and write operations.
• Filling and fixing the verification bugs.
• Debugged and trace back issues using Sim-Vision tool.
• Assigned to create test cases to verify the BUS and Interrupts.

Role & Responsibility: -Router client: - D-link

• Verified the RTL module using in Verilog code an PLD (Programmable Logic Devices).
• Generated Functional Coverage and code coverage for the design.
• Monitor bugs using developed test cases and report
• Generated toggle coverage reports to evaluate change in signals.
• Ability in creation of verification environments using a System Verilog