Summary
Work History
Education
Skills
Timeline
Generic

Sunku Suneel

Kadapa

Summary

Four years of experience in physical design with a focus on floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure. Proven track record of addressing challenges in 2nm, 4nm, and 16nm technologies, optimizing designs to minimize congestion and improve timing results. Expertise in delivering high-quality designs that meet stringent performance criteria.

Work History

Accenture
- Current
  • Overall experience of 4 years in Physical Design.
  • Previous Company names: Frenustech, Keenheads.
  • Current Company name: Accenture (ExcelMax).

Qualcomm

Contributed to six tapeouts at Qualcomm, specifically for Shikra project in DDR team using 4nm technology.

  • Executed complete P&R processes, including floorplan, power planning, place & route, and timing analysis.
  • Conducted multiple floorplan experiments to reduce congestion and improve timing performance.
  • Addressed timing issues by applying weightage efforts and creating path groups for enhanced results.
  • Manually routed numerous nets on higher layers to mitigate high crosstalk noise.
  • Ensured closure of all signoff checks, including PV, PDN, FV, and CLP.

Qualcomm
  • Executed implementation of tunnels and various super buffers to drive project success.
  • Overcame significant PG and routing challenges with limited track resources.
  • Delivered zero shorts and zero opens in database as per project timeline.
  • Focused on secondary power domain routing across complex multilevel blocks.
  • Improved timing through strategic cell swapping and drive strength modifications.
  • Ensured proper signal routing and shielding on both tunnels for enhanced performance.
  • Completed all required signoff checks including PV, PDN, FV, and CLP evaluations.
  • Addressed cross-talk issues to optimize overall design integrity.

Fermionic Design
  • Technology: 16nm
  • Challenges:
  • Did implementation of Floor Planning, Placement, CTS, Routing, Running ECO, Cleaning DRV issues at block level.
  • Did Experiments for best macro placement to get good logic distribution to avoid congestion issues by proper blockages & cell padding.
  • worked on timing closure and PDN related issues.
  • Knowledge on resolving various block level PnR issues.

Frenustech
  • Client: UMC
  • Technology: 16nm
  • Responsibilities: To implement Netlist, Floorplan to Routing and PVChecks.
  • Challenges:
  • Mu Multiple experiments have been tried for floorplan and blockages has been added based on congestion analysis.
  • Did Experiments for to get good logic distribution in placement stage.
  • CTS building to meet minimum skew and clock tree optimization.
  • worked on block level drc and shorts.
  • Made some automated scripts to reduce the time consumption for the deliverable.

Education

B. Tech -

Annamacharya institute of technology and sciences
01-2020

PU -

Narayan junior college
01-2016

SSC -

Deepthi High School
01-2014

Skills

  • VLSI physical design
  • Floorplan development
  • Placement optimization
  • Clock tree synthesis
  • Routing techniques
  • Timing closure strategies
  • Signoff verification
  • Innovus tool proficiency
  • TCL scripting skills

Timeline

Accenture
- Current

Qualcomm

Qualcomm

Fermionic Design

Frenustech

B. Tech -

Annamacharya institute of technology and sciences

PU -

Narayan junior college

SSC -

Deepthi High School
Sunku Suneel