Tushin Shrotriya

SoC design and integration (10/2020 - Present)

Responsibilities taken:

• Handling database and delivering high quality SoC RTLs.
• Finishing connectivity for all the cores from SoC level perspective.
• Cleaning up all the compilation checks which are run on various tools from different vendors to ensure 100% quality.
• Cleaning up elaboration and running entry level DV (Design Verification) checks for a quick turnaround before passing the RTL to DV.
• Creating ECO (Engineering Change Order) scripts and implementing it at SoC as well as providing the same to cores, if needed.
• Working with the PLDRC/CDC team to close on any issues related to SoC as well as help them in closing the core related issues.
• Collaborating with various teams such as Power, Clock, Core-level design team etc. and ensure a high quality SoC RTL.
• Coming up with new ideas for automation to reduce manual effort and the time spent by the team.

SoC PD CLP and FV sign-off (07/2017 - 10/2020 )

Tasks performed for CLP (Conformal Low Power):

• Proper review of DC (Design Compiler) reports with the synthesis team to ensure clean collateral transfer from DC to PD (Physical Design).
• Collaborated with the HM CLP signoff PoC for smooth SoC flat CLP closure.
• Ensured correct power domain FT (Feed-Through) punching through sub-HMs by working with SoC floorplan team.
• Working with SoC Power signoff team to ensure quality UPF (Unified Power Format) delivery.

Tasks performed for FV (Formal Verification):

• Proper review of DC reports with the synthesis team to ensure clean data transfer from DC to PD.
• Collaborated with PD teams (SoC and HMs) for smooth FV closure.
• Ensured correct FT punching through sub-hms by working with SoC Floorplan team
• Collaborated with HM FV sign-off PoC for ease in closing SoC level Flat FV.
• Proper extraction of HM level constraints to be used at the SoC level for smooth FV closure.
• Set up proper DFT (Design For Test) constraints and had them properly reviewed with DFT team.
• Set up modelling options for efficient use of resources such as memory and runtime.

Tasks performed at this position are the same as mentioned in the ' SoC PD CLP and FV sign-off' section above.