Uday Bathula

Working on 4nm node from RTL to GDS-II.

One tile had 95 memories, need to run synthesis on DC which had violated already in Synthesis.

Tile is very critical to meet reg2mem & reg2reg due to macros delay & logic depth.

Another is a top tile which had IO pads, PLL, Efuse, sub-tile & 700 macros, which is quite difficult for FP.

Working on different FP experiments to get better result.

Worked 6nm, 7nm(TSMC) 12nm(SMIC), 14nm(GF), node projects.

Handled Hierarchical blocks, multi-voltage blocks and Macro blocks and can do all the stages like Floor Planning, Placement optimization, CTS and Routing to timing closure.

For Hierarchical blocks did Partitioning, Pin Placement& Mapping, Manual clock Built, Clock Balancing.

I also have 3-year experience in Physical Verification.

Did all sign-off checks like block level & Hierarchical Blocks Timing closure in ECO stage and all Physical Verification check like DRC, LVS, ERC and FM.

Hands on experience tools like Innovus, Genus, Prime time, Calibre.

Worked on Metal ECOS & Closed them.