Vaibhav Tripathi

Proposed design changes to improve performance and operational capabilities of existing IP blocks.

• Bring-up, developed and maintained 2 blocks for IP verification architecture, testbenches, tests and infrastructure.
• Developed and debugged test plans using system Verilog and UVM constrained -random test methodology, directed test methodology to implement and maintain testbenches and tests.
• Setting up regression, debug simulation, analyze coverage, work and resolve technical issues with design to achieve verification coverage.
• Worked on reusable test methodology across multiple IPs.

Project Profile (#1) Security IP Maintenance (10 Months)(Intel CW)

This Project involves scoreboard and checker development and verifying through Unit Level Testing

• Responsibilities included developing checkers (on basis of HAS and MOAT) and scoreboard, verifying it by unit Level Tests,
• Worked on unit level test environment and to understand scoreboarding primarily.

Project Profile (#2) Testchip Framework Project (8 Months) (Intel CW) (SoC Verification)

This Project involve Pre-Silicon Validation for Testchip Framework

• Worked on Gate Level Simulation to set-up, running and maintaining regression and debugging failed tests.
• Developing SPFs files according to High Level Architecture and specification, verifying functionalities.

Project Profile (#3) PSG TIP4 Project (7 Months)(Intel CW)

This project involves in verification of different blocks of PSG TIP4,

• Running regression for coverage for DMA and top blocks and reporting results to client.
• Running full regression and sending failed tests primary analysis by Verdi to PoC.
• Worked as buffer resource in case of any requirement