Vinay Kumar Arroju
VLSI Physical Design Trainee
Hyderabad
Summary
A Highly motivated and passionate VLSI Physical Design Engineer determined to achieve better PPA (Performance, Power,Area)
Overview
1
1
Certification
2027
2027
years of professional experience
Work History
Major project
Physical Design Trainee
Sumedha Institute of Technology
12.2025 - Current
- Hands on experience in DC compiler synthesis and ICC2 for pnr.
- Applied SDC constraints for fixing timing issues like WNS and TNS.
- Betterment of timing and fixing setup voilations by analyzing reports of timing and QOR
- Core creation and ports placements and fixing pin placement issues at floorplan.
- Fixing DRC violations and missing vias at PG mesh creation.
- Fixing legality issues at placement
- Reducting high congestion red hotspot areas
- Achieving Clock tree balancing by honoring target skew and target latency
- Fixing hold voilations at CTS
- Fixing DRVs and LVS issues at Routing
- Betterment of PPA
Education
B.Tech - Electronics & Communication Engineering (ECE)
JNTUH College of Engineering Rajanna Sircilla
Sirsilla, India06-2025
INTER -
Narayana Junior College
03-2020
SSC -
Ratnam Global High School
03-2018
Skills
RTL-to-GDSII Physical Design Flow
Floorplanning & Core Utilization
Power Planning (Basics)
Standard Cell Placement & Optimization
Clock Tree Synthesis (CTS)
Certification
VLSI Physical Design Training – Sumedha Institute of Technology, Hyderabad (Ongoing since Dec 2025).
Timeline
Physical Design Trainee
Sumedha Institute of Technology
12.2025 - Current
Major project
B.Tech - Electronics & Communication Engineering (ECE)
JNTUH College of Engineering Rajanna Sircilla
INTER -
Narayana Junior College
SSC -
Ratnam Global High School