Akhilesh Sharma
Senior Design Engineer
Noida
Summary
I have been working in a field which is at the intersection of Artificial Intelligence and Hardware for past 4 years. During this period I have learnt that AI hardware is a full stack problem which requires skills in both hardware and software. I have keen interest in both hardware, deep learning software models and am looking for opportunities where I can use these skills to contribute towards building more advanced AI hardware.
Overview
4
4
years of professional experience
Work History
Senior Design Engineer
STMicroelectronics
Greater Noida
11.2020 - Current
- Understood and modified an open source PyTorch based In-Memory Compute framework for Quantization Aware Training and Noise Modelling to generate input vectors and reference output vectors for Analog In-memory Compute subsystem using 4-bit Quantized CNN models like ResNet18, VGG16 etc.
- Ported complete verification environment to emulation platform for faster verification cycle of upcoming SOC projects and accelerating the development of the software stack.
- Performed PLL Bring up of the SOC and generated functional test patterns for post silicon validation.
- Functional verification of Digital In Memory Compute (DIMC) SOC. I was responsible for creating the test plans, generating C-based integration tests for the SOC, functional tests for the DIMC subsystem, debugging, and performing zero-delay and back-annotated simulations.
- Created complete flow for performing power analysis for benchmarking digital NPU by running end-to-end compiler generated C tests for complete CNN architectures using Emulation platforms. RTL activity extracted through the emulation which was used to do perform power analysis.
- Performed Logic Synthesis of the RTL used for benchmarking to generate netlist for power analysis.
Design Engineer
STMicroelectronics
Greater Noida
06.2018 - 11.2020
- Defined BIST strategy and integrated it for memories of digital NPU which was integrated into an Automotive SOC to add close to 1TOPS of neural processing capability to the leading automotive product of ST.
- Performed integration, functional and BIST tests for the NPU subsystem integrated into the SOC.
- Functional verification of AI SOC having two key components, NPU and SRAM based In-Memory Compute, which was first silicon in the company with In-memory compute adding 4TOPS of quantized neural network capabilities to an STM32 class product template. Created C based directed tests for verifying the convolution accelerator.
- Defined BIST strategy and integrated BIST for this SOC and performed BIST integration as well as functional tests.
- Created C based reference model for the convolution accelerator present in NPU.
- Performed Logic Synthesis of the design, performed analysis of timing reports at different PVT corners.
Intern
STMicroelectronics
Greater Noida
01.2018 - 06.2022
- Synthesis of a complete design using ST synthesis flow. Understood the how to define timing constraints, use different PVT corners for synthesis.
- Designed 32Kx32 single port memory using 512x16 dual port memory using Verilog HDL.
- Designed Asynchronous FIFO using dual port memory in verilog.
- Implemented FIR filter in C language.
Education
B.E. - Electronics And Communications Engineering
Thapar Institute of Engineering And Technology
Patiala 06.2014 - 06.2018
Skills
Digital Electronics
Interests and Hobbies
- Deep Learning: I have keen interests in fast evolving deep learning models. I have also built some basic applications to gain knowledge of how deep learning works.
- Link for my Github account: www.github.com/sharmaa4
- Music.
Timeline
Senior Design Engineer
STMicroelectronics
11.2020 - Current
Design Engineer
STMicroelectronics
06.2018 - 11.2020
Intern
STMicroelectronics
01.2018 - 06.2022
B.E. - Electronics And Communications Engineering
Thapar Institute of Engineering And Technology
06.2014 - 06.2018
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