ANUBHAVKUMAR SHUKLA
Bengaluru
Summary
Senior Lead Verification Engineer specializing in large-scale, performance-critical hardware IP verification. Expertise in SystemVerilog and UVM with comprehensive ownership from testbench architecture to coverage closure. Collaborates effectively with design teams to resolve issues and deliver production-ready IPs through efficient regression infrastructure.
Overview
1
1
Certification
7
7
years of professional experience
Work History
Lead Engineer, Senior
Qualcomm India Pvt Ltd
Bengaluru
02.2025 - Current
- Led verification for large-scale, performance-sensitive IP - CENG, collaborating with design teams on debug and issue resolution, while maintaining stable UVM-based regression infrastructure to ensure consistent quality and timely delivery.
- Owned end‑to‑end IP verification for Huffman IP, including defining scalable UVM testbench architecture, developing constrained‑random and directed tests in SystemVerilog, driving functional and code coverage, and achieving final sign‑off quality.
- Contributed to verification of bandwidth-efficient, performance-critical hardware IP - UBWC using SystemVerilog and UVM, developing expertise in compression workflows, complex data paths, and high-throughput corner scenarios.
Sr. Design Verification Engineer
Intel India Pvt Ltd
Bengaluru
06.2019 - 01.2025
- Contributed to GFX pipe development by focusing on Vertex Fetch, Vertex Shader, Tessellation, Windower, and Clipper units.
- Resolved Handle checker and scoreboard issues through systematic debugging and fixes.
- Developed debugkey based post-processing checkers, for GFX units to assist in debugs.
- Coded SV Assertions for assertion based verification.
- Worked on functional coverage and coverage analysis.
- Owned and delivered bring up, clean up, execution & validation of multiple different features during various projects over the years.
- Engaged in development of comprehensive test plans based on requirements analysis, ensuring thorough coverage of design functionality.
- Streamlined operations by creating perl scripts to automate tasks such as bulk regression and weekly disk space checks.
- Maximized functional coverage by implementing targeted tests and simulations to reduce risks of undetected defects.
- Ensured timely completion of projects by effectively managing resources and prioritizing tasks according to project objectives.
- Implemented code reviews and quality checks to maintain high standards of coding practices within the team.
Education
MTech - E&ECE
Indian Institute of Technology (IIT)
Kharagpur01-2019
B.E. - E&ECE
DY Patil's Ramrao Adik Institute of Technology
Nerul01-2016
Skills
- SYSTEM VERILOG
- UVM
- SYSTEM VERILOG ASSERTIONS
- VCS tool
- Functional and Code Coverage
- VERDI BY SYNOPSYS
- PYTHON
- PERL
- ClearCase Tool
Certification
- UVM (Universal Verification Methodology) course, Cadence
- Essential SystemVerilog for UVM
Accomplishments
- Presented a poster for self-checking mathematical model for efficient verification in multi core graphics architecture at Intel CGAI INDIA Tech Summit, 07/01/24
- Appreciation from INTEL PEs for Conducting a training session on 'System Verilog for Verification' for new interns/college graduates., 08/01/24
Timeline
Lead Engineer, Senior
Qualcomm India Pvt Ltd
02.2025 - Current
Sr. Design Verification Engineer
Intel India Pvt Ltd
06.2019 - 01.2025
MTech - E&ECE
Indian Institute of Technology (IIT)
B.E. - E&ECE
DY Patil's Ramrao Adik Institute of Technology