ANWESHA SWAIN
BENGALURU
Summary
Results-driven Design Verification Engineer specializing in UVM-based environments for camera and DDR subsystems at SoC level. Expertise in constrained-random verification, assertions, functional coverage, and performance verification. Skilled in VIP integration, debugging complex multi-IP issues, and regression automation. Proven experience in pre-silicon verification and cross-functional collaboration with design and architecture teams.
Overview
8
8
years of professional experience
1
1
Certification
Work History
Design Verification
Qualcomm
Bangalore
07.2022 - Current
- Developed and debugged UVM-based verification environments for camera pipeline IPs using SystemVerilog
- Analyzed design and architecture specifications to derive verification scenarios, and contributed to test plan creation, regression planning, and failure triage
- Implemented constrained-random stimulus, assertions (SVA), and functional coverage for feature verification
- Worked on testbench bring-up and enhancements, including sequence updates and checker improvements
- Debugged issues related to backpressure, data flow, and pipeline latency using RTL waveform analysis
- Designed and executed performance (perfmon) and stress tests for camera processing pipeline components
- Implemented latency tracking and performance validation across multi-stage data processing pipeline
- Contributed to regression debug, failure triage, and coverage closure across multiple features
- Integrated and debugged CDC assertions during technology node migration and collaborated on root-cause analysis
- Automated regression and backward compatibility verification flows using Python/Perl scripting
- Worked on DDR subsystem verification including memory controller behavior, cache interaction, and bandwidth validation
- Verified DDR bandwidth and latency scenarios and correlated performance across SoC data paths
- Supported DDR bring-up on emulation and post-silicon platforms, validating initialization and data traffic behavior
- Performed post-silicon debug and performance correlation between pre-silicon verification and silicon measurements.
Verification and Validation Engineer
Collins Aerospace
Bengaluru
08.2018 - 06.2020
- Worked on Embedded C based software verification for Brake Control Unit (BCU), including requirement-based testing and debug
- Performed development testing on MPC5554 microcontroller using TRACE-32 and supported software integration
- Ensured MISRA-C compliance and followed DO-178 avionics software guidelines
Education
ME - Embedded System and VLSI
BITS PILANI
Pilani06-2022
BTECH - ECE
KIIT university
Bhubaneshwar03-2018
Skills
- UVM
- SystemVerilog
- Verilog
- Assertions (SVA)
- Constrained Random Verification
- Functional Coverage
- Coverage Driven Verification
- UVM Testbench Architecture
- RTL Debug (Waveform Logs)
- Synopsys VCS
- Verdi
- Trace32
- Emulation / FPGA bring-up exposure
- Camera/Image Processing Pipeline
- DDR Subsystem
- AXI / AHB
Certification
- System Verilog for Verification-Projects, https://www.udemy.com/certificate/UC-6692c0eb-a612-42c1-9ca2-d3a76c381891/
- Verilog for Verification-Fundamentals, https://www.udemy.com/certificate/UC-ad1b452e-6c68-4869-b504-8c4885e9e40d/
Accomplishments
Best Poster Presentation award in QBUZZ-2023 conference for the topic 'DDR Bandwidth Optimisation by efficient
usage of system cache for caching multimedia based clients such as video and camera'
usage of system cache for caching multimedia based clients such as video and camera'
Timeline
Design Verification
Qualcomm
07.2022 - Current
Verification and Validation Engineer
Collins Aerospace
08.2018 - 06.2020
ME - Embedded System and VLSI
BITS PILANI
BTECH - ECE
KIIT university