Summary
Work History
Education
Skills
Accomplishments
Languages
Positions Of Responsibility
Projects Ongoing
Projects Completed
Developer Tools
Areas Of Interest
Databases
Workshops Training Conferences
References
Training Placement Office
Hobbies and Interests
Disclaimer
Timeline
Generic

ARYA SINHA

Summary

Analog Electronics Enthusiast with a strong foundation in electronics engineering. Eager to leverage my theoretical knowledge and passion for analog circuits to contribute to real-world applications. Seeking an opportunity to learn from experienced engineers and contribute to innovative analog design projects

Work History

Indian Institute Of Technology (B.H.U)
  • Duration: Dec 2023 - Jan 2023
  • Implemented a 4-bit full adder, a counter ranging from 0 to 9, and subsequently employed multiplexing logic to extend the range to 00 to 99, then 000 to 999, and finally 0000 to 9999,Designed a digital clock to represent real-time in the format - h2h1.m2m1:s2s1, and currently working on a keyboard LCD interface

Entuple Technologies Pvt. Ltd.
  • Duration: May 15 - July 28, 2023
  • Physical Design & Verification Using Verilog(Cadence) Remote Training - Completed a comprehensive 4-week training program focused on gaining proficiency in the areas of PD flow, floor and power planning, placement, clock tree synthesis, physical verification, and timing fixes

Nelumbus Technology
  • Duration: June 2, 2023 - July 31, 2023
  • Software Developer Intern Remote - QPChampion : Worked in a team and contributed to the development of a user-friendly question paper generator application

Education

B.Tech - Electronics and Communication Engineering

National Institute of Technology Mizoram

Senior Secondary - Science

Surndranath Centenary School
CBSE
07.2020

CISCE -

Mount Carmel School
05.2018

Skills

  • Cadence EDA Tool
  • Xilinx Vivado
  • Synopsys TCAD Simulator
  • Multisim
  • MATLAB
  • Basys3
  • Nexys 4 DDR
  • LaTeX
  • Microsoft Office Suite
  • Linux (REDHAT, CentOS, Ubuntu)
  • Digital System Design with FPGA
  • Semiconductor Device Simulation
  • Analog and Digital Circuit Design
  • VHDL
  • Verilog
  • C
  • Java
  • HTML
  • CSS
  • JavaScript

Accomplishments

  • Panel Discussion at Y20 Inception Meet: Participated in discussions on climate change, youth in politics, Industry 4.0, health, and peace-building with Honorable Minister of Youth Affairs and Sports, Government of India, and experts at IIT Guwahati and Hotel Radisson Blu (February 2023).
  • 1st Prize in Basketball Tournament: INTER ICSE SPORTS EVENT (2017)
  • Prabhat Khabar Bal Pratibha Samman: Awarded in 2018

Languages

English
Hindi

Positions Of Responsibility

  • Represented India at Y20: Ministry of Youth Affairs & Sports Official Delegate of Youth 20 (Y20), Youth Engagement Group of G20
  • Captain of Basketball Team: Represented as captain of basketball team at INTER ICSE SPORTS EVENT and led the team to victory

Projects Ongoing

  • MAC accelerator map | FPGA: Executed a project implementing a Convolutional Neural Network (CNN) for image processing on a Field-Programmable Gate Array (FPGA). This involved the strategic mapping of a Multiply-Accumulate (MAC) accelerator onto the FPGA. The project required the storage of 24x24 dimension images on a memory card, from which pixel weights were extracted and efficiently stored in BlockRAM. The CNN was further optimized using activation functions such as Rectified Linear Unit (ReLU) and Sigmoid. This research underscores my adeptness in applying advanced concepts in digital electronics and machine learning to solve complex, practical problems.
  • Keyboard-LCD Interface | FPGA: Executed a project implementing a stem to capture keyboard inputs and display them on an LCD using a Basys3 FPGA board. The design, implemented in Verilog and simulated and tested with the Vivado Design Suite, integrated UART, SPI, and I2C protocols for seamless communication between the keyboard, LCD, and FPGA. The Basys3 FPGA board's inbuilt 100MHz clock was strategically divided to a 1ms time period for simultaneous column checking in the keyboard. Additionally, a debouncing technique was employed to ensure accurate value capture from the keyboard. This project highlighted my ability to design and implement complex hardware interfaces, manipulate clock frequencies, and apply advanced concepts like debouncing for enhanced system performance.
  • Design and simulation of Capacitorless Compact memory design | Synopsys TCAD Simulator : The new concept of Zero-capacitor DRAM (Z-RAM) based on the bipolar transistor present in the MOSFET has been reported and exhibited low power, high speed, and improved data retention time. The ultimate advantage of this new concept is that it does not require a capacitor, and, in contrast to traditional 1T/1C DRAM cells, it thus represents a 1T/0C cell named Z (for zero)-RAM. The new devices also been introduced to replace MOSFET. The Zero capacitor RAM can also designed using Double gate, junction less, FinFETs and Thyristor based devices..

Projects Completed

  • Analog/Digital Circuit Design and Simulation| Cadence Design Tool , feb 2024- May 2024: Designed and simulated Common Base (CB), Common Emitter (CE), and Common Collector (CC) amplifiers.Created and tested the functionality of a CMOS inverter, Examined the voltage transfer characteristics (VTC),Implemented and validated a two-input NAND gate.
  • Design and Implementation of High Speed UART | Basys3, Aug 2023 - Nov 2023: A full duplex (Receive and Transmit at the same time) UART design with a transmission speed of 2.92Mbps using Verilog. Complete UART design was simulated on Xilinx Vivado 2019.1 and implemented on Basys3 FPGA Board.
  • Digital Clock | Nexys 4 DDR, Dec 2023 - Jan 2024: Utilized my expertise in Verilog and the Vivado Design Suite to engineer a digital clock on a Basys3 FPGA board. The project encompassed the creation of synthesizable Verilog code for the clock's functionality, which was subsequently simulated and validated using Vivado's extensive toolset. The final design was successfully deployed on the Basys3 FPGA board, showcasing my capacity to manage a hardware design project from ideation to physical realization. The Basys3 FPGA board's inbuilt 100MHz clock was ingeniously divided to achieve a 1Hz frequency for a one-second counter and a 10ms period to optimize the perception of vision for LEDs. This project underscored my ability to manipulate clock frequencies effectively for desired outcomes.

Developer Tools

  • MATLAB
  • GitHub
  • NetBeans
  • Visual Studio Code
  • IntelliJ IDEA

Areas Of Interest

  • Solid State Devices
  • VLSI
  • Digital Logic Design
  • Analog Circuits

Databases

  • MySQL
  • MongoDB

Workshops Training Conferences

  • Sensors Application Workshop,NIT Mizoram March 2023
  • Geodata Processing using Python,IIRS-ISRO, Dehradun February 2023
  • Y20 India Inception Meet,Official Youth Engagement Group of G20 February 2023
  • JAVA, Data Structure, And Algorithm Course,PW Skills Ongoing Since 2022
  • System Design Course,PW Skills Ongoing Since 2022

References

  • Professor (Dr.) S. Sundar, Director NIT Mizoram, Professor Department of Mathematics, Indian Institute Of Technology Madras, India, director@nitmz.ac.in
  • Dr. Pragati Singh, Assistant Professor, Dept. of Electronics & Communication Engineering, NIT Mizoram, pragati.ece@nitmz.ac.in, +91-8119966847
  • Rahul Daraad, Principal Product Validation Engg, Cadence Design Systems, 55 Network Dr, Burlington, MA 01803, drahul@cadence.com, +12016470608

Training Placement Office

Training and Placement Office NIT Mizoram

Hobbies and Interests

  • Coding
  • Painting
  • Playing Basketball
  • Shot put

Disclaimer

I hereby declare that the entries in this Curriculum Vitae are true to the best of my knowledge and belief.

Timeline

Indian Institute Of Technology (B.H.U)

Entuple Technologies Pvt. Ltd.

Nelumbus Technology

B.Tech - Electronics and Communication Engineering

National Institute of Technology Mizoram

Senior Secondary - Science

Surndranath Centenary School

CISCE -

Mount Carmel School

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