ASHISH KUSHWAHA
Bengaluru
Summary
Highly motivated SoC Verification Engineer with 4+ years of experience in developing and executing verification solutions for complex SoCs. Skilled in UVM, SystemVerilog, and C, with expertise in functional verification and testbench architecture. Collaborated with cross-functional teams to deliver silicon-ready designs on schedule, while continuously applying industry best practices.
Overview
9
9
years of professional experience
Work History
Senior SoC Design Verification Engineer
NXP Semiconductors
Bengaluru
04.2025 - Current
- Owning end-to-end UVM testbench development, from initial architecture to regression automation and maintenance, for a subsystem in a SoC verification project.
- Led creation and integration of reusable testbench components-drivers, monitors, scoreboards-improving environment modularity and reducing verification cycle time.
- Expertise in verifying Audio peripherals like SAI and MQS.
- Created vplans and contributed to the development of verification IP.
- Performed root cause analysis and debug of complex functional failures.
- Collaborated with Architecture, design verification teams to improve verification efficiency and quality.
SoC Design Verification Engineer
NXP Semiconductors
01.2022 - 03.2025
- Performed end-to-end functional verification of owned blocks spanning from Architectural specification understanding, Vplan creation and review, testcase coding and debugging to coverage closure for multiple SoC
- Expertise in verifying various memory controllers like DMA and SRAM controller.
- Expertise in verifying peripherals like FlexCAN, FlexTimer and General Purpose timer.
- Wrote directed and constrained-random test cases to achieve high functional and toggle coverage.
- Developed and performed formal connectivity checks for owned modules.
- Worked on identifying and resolving X-propagation issues in Gate-Level Simulations
Assistant Engineer
Ericsson India Global Services Pvt. Ltd
Noida
03.2017 - 03.2019
- Oversee daily NOC operations, ensure SLA compliance, manage real-time MW activities, and coordinate with stakeholders for updates and resolution of critical incidents.
- Generate trouble tickets and Major Incident Notifications for faulty nodes and coordinate field engineers for on-site planned work.
Education
M.E - Microelectronics
BITS Pilani
06-2022
B-Tech - Electronic and Communication
AKTU
Lucknow06-2016
Skills
- Verification - Architecture specification analysis, Vplan creation, Constraints, SV Assertions, Waveform analysis, formal CC, Coverage analysis
- Verification Methodologies - UVM
- Hardware Description Languages - Verilog, System Verilog
- Verification Tools - Verdi, VCS, VCFormal
- Protocols Experience - AXI, AHB, APB
- Programming Language - C, Python Basics
Hobbies
Travelling, Table Tennis, Badminton
Timeline
Senior SoC Design Verification Engineer
NXP Semiconductors
04.2025 - Current
SoC Design Verification Engineer
NXP Semiconductors
01.2022 - 03.2025
Assistant Engineer
Ericsson India Global Services Pvt. Ltd
03.2017 - 03.2019
M.E - Microelectronics
BITS Pilani
B-Tech - Electronic and Communication
AKTU