BHASKARA RAO VANTAKU
Accomplished RTL Design Engineer with expertise in Verilog and VHDL, successfully delivering high-performance digital circuits at Apollo Micro Systems. Demonstrated strong collaboration skills while integrating hardware and software, and excelled in debugging and optimizing designs. Proven ability to enhance design efficiency and ensure compliance with specifications through rigorous testing and analysis.
Work History
RTL DESIGN ENGINEER
3 Years 3 Months- Designed and implemented RTL code for high-performance digital circuits using Verilog/VHDL.
- Performed logic synthesis, timing analysis, and functional simulation to ensure design compliance with specifications.
- Developed BOMs and technical documentation for manufacturing teams.
- Reviewed schematics and models for fit, function, and assembly.
- Researched feasibility, design or performance of components or systems.
- Designed Schematics of STM32H7A3ZIT6Q Controller Hardware design in ORCAD Capture .
- Developed VHDL and Verilog drivers for AXI, I2C, SPI, and UART protocols.
- Developed NOR Flash verilog driver and used AXI EPC IP and AXI GPIO IP in VIVADO
- Implemented the Ethernet protocol using 1G/2.5G Ethernet subsystem IP and Ethernet lite IP in Vivado.
- Tested and debugged existing code to identify performance issues.
- Collaborated with a cross-functional team to integrate hardware and software, utilizing strong teamwork and collaboration skills
Advanced VLSI Design for Testability Course
10 MonthsEducation
B.Tech - Electronics and Communications Engineering
Diploma - Electronics and Communications Engineering
Matriculation
Skills
Certification
- Industrial training, 05/2018 - 11/2018, Basics of PCB designing, basics of embedded system.
- Career Edge, 04/2020 - 05/2020, Communication skills, soft skills, presentation skills.
Accomplishments
District Level Poly Techfest, 09/2018, Got 1st place for Moisture based automatic irrigation system project.
Projects
Router 1x3 – RTL design and Verification
The router accepts data packets on a single 8-bit port and routes them to one of the three output channels, channel0, channel1 and channel2. Architected the block level structure for the design. Implemented RTL using Verilog HDL. Verified the RTL model using System Verilog. Generated functional and code coverage for the RTL verification sign-off. Synthesized the design.
ATM Security Using GSM and MEMS Sensor
Whenever robbery occurs, MEMS sensor is used here which senses the movement of ATM machine. A tri band GSM is used to send the message to the vigilance team and for the respective bank authorities. When the movement of machine is sensed by the MEMS sensor the beep sound will occur from the buzzer which acts as an alerting device. A DC Motor is used for shutting the door.
Hobbies and Interests
- Travel
- Sports
- Listening to music
- Video editing