Sriprudhvi

FPGA & ASIC Design with 5 years 6 Months of experience in designing, debugging and testing FPGA & ASIC based digitalsystems with SOC. Proficient at writing Verilog design sources, Verilog testbench sources, C based application projects for SoC. Designed and verified FPGA system with Verilog sources on Spartan ,Virtex, Artix ,Zynq Xilinx toolsand compiling , LINT and Synthesis with Synopsy Design tools .Possess excellent communication skills and ready to work in a challenging environment.

ECIL, 08/16

• Telugu
• English
• Hindi

8 Months, UC4 & RS9, Capgemini, Hyderabad, MCHP, Implemented padding changes to enhance the performance of compiling, building, and simulating processes., Conducted system-on-chip (SoC) checks to ensure functionality and compatibility., Managed and executed RDC changes to optimize system operations., Parttool, Verilog, 08/01/23 to Present 12 Months, AXON, Altran, Hyderabad, Telechips, South Korea, Integrated IPs to top level NOC to enhance system functionality and performance., Resolved RTL issue through debugging, ensuring seamless operation of the system., Conducted LINT and Synthesis to the modules to maintain design integrity and optimize performance., Synopsys, Verilog, 05/09/22 to 03/23 3 Months, RAM verification, LTTS, Chennai, L&T, Support to the Verification Team., SV, UVM, 10/21 to 12/21 6 Months, Mill interface, VTPL, Hyderabad, BEL, INDIA, Design and test the functionality., ISE, EDK, Verilog, 11/20 to 04/21 9 Months, ESMP, VTPL, Hyderabad, DLRL, INDIA, Design the functionality., Debugging the RTL issue., Clear the Ethernet Issues., Debug design into hardware., Vivado, Verilog, 04/20 to 12/20 6 Months, TDF, VTPL, Hyderabad, BEL, INDIA, Debug the design., Functionality testing., ISE, System Verilog, 08/19 to 01/20 4 Months, TEST JIG, VTPL, Hyderabad, DLRL, Design using Verilog., Debug the design., Functionality testing., ISE, EDK, SDK, Verilog, 03/19 to 06/19

3 Months, Electronics Corporation of India (ECIL), VLSI Digital Electronics, VEDIC Multiplier Design Simulation and Debugging

Total Experience: 5 Years 5 Months