C G Vennela
Bangalore
Summary
4+ years experienced working professional in VLSI Front End Pre- Silicon Verification of IP, Subsystem and SOC. Proficient in developing test plans and industry standard languages such as System Verilog, Verilog. Experience in UVM based simulation verification as well as Formal Verification.
Overview
5
5
years of professional experience
Work History
Engineer - II
Cientra Part of Accenture - Client(Qualcomm)
09.2021 - Current
- Worked as a DV Engineer for multiple mobile/modem/auto projects for various blocks using both simulation UVM based methodologies.
- Debugging the issues related to block.
- Developed new test cases for new features to be verified at the block level.
- Design Verification test plan based on functional specification with estimated timelines for verification completion.
- Good in verification planning till Sign off closure using coverage driven metrics.
- Hands on experience in developing system Verilog UVM verification environment from scratch with functional coverage, assertion and constrained random stimulus.
- Formal connectivity verification as well as FPV .
- Package Verification of the chip.
- Debugged failures in RTL simulations and GLS.
Design Verification Engineer
Bitsilica | Cientra - Client(Qualcomm)
07.2021 - 02.2024
- Testbench enhancement in SOC simulation.
- Formal testbench setup development for IP verification.
- Testcase development for RTL, New feature verification.
- Functional coverage, Toggle coverage enablement and closure.
- Power aware testcase development and deployment.
Junior Engineer
Raiton Semicoductors Client(Intel)
06.2019 - 07.2020
- Responsible for understanding specification.
- Developed System Verilog based Verification environment.
- Involved in writing the test sequence and reported RTL bugs.
- Involved in debugging Regression failure testcases.
- Functional coverage closure.
Education
Bachelor of Technology - Electronics And Communications Engineering
JNTUA Affiliated CREC College of Engineering
Tirupati, AP05.2018
Diploma - Electronics And Communications Engineering
SV College of Engineering & Technology
Chittoor, AP05.2015
Skills
- HDL/HVL Languages - Verilog, System Verilog
- HVL Methodology - UVM
- Formal Verification
- Protocols - PCIe, AMBA AXI, APB, AHB
- Tools - Synopsys VCS, VCF, Verdi, Clearcase
Timeline
Engineer - II
Cientra Part of Accenture - Client(Qualcomm)
09.2021 - Current
Design Verification Engineer
Bitsilica | Cientra - Client(Qualcomm)
07.2021 - 02.2024
Junior Engineer
Raiton Semicoductors Client(Intel)
06.2019 - 07.2020
Bachelor of Technology - Electronics And Communications Engineering
JNTUA Affiliated CREC College of Engineering
Diploma - Electronics And Communications Engineering
SV College of Engineering & Technology
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