Charan Sai Sudula
Bengaluru
Summary
Verification IP Engineer at Synopsys with hands‑on experience in AMBA CHI, CHI‑C2C, and AHB Verification IP development, including feature implementation, UVM‑based testbench creation, protocol checks, and functional coverage closure. Proficient in SystemVerilog, UVM, and debugging complex protocol issues.
Overview
4
4
years of professional experience
2
2
Certifications
Work History
R&D Engineer, Verification IP
Synopsys
Bengaluru
08.2023 - Current
- Currently working on AMBA system-level verification components involving CHI, CHI‑C2C, and AHB protocols in an SV‑UVM–based environment.
- Played a key role in the ground‑up development of the CHI‑C2C Verification IP, contributing to the implementation of core protocol logic from the specification phase through the first customer release.
- Worked on implementing multiple enhancements and resolving customer‑reported issues for the AMBA CHI, CHI‑C2C, and AHB Verification IPs. Involved in developing and validating new specification features.
Designed and developed UVM‑based verification environments, including sequencer, driver, monitor, and scoreboard, along with protocol checkers, sequences, verification plans, and functional coverage closure. - Debugged complex protocol issues using waveform analysis, protocol analyzers, and logs, ensuring the correctness and robustness of the VIP.
R&D Intern, Verification IP
Synopsys
Bengaluru
08.2022 - 07.2023
- I have worked on AHB, APB, and ATB Verification IPs, implementing customer‑requested enhancements and resolving reported bugs. I improved the coding messages to simplify debugging. I also created several self‑checking (negative) tests to validate new features and protocol checks.
Education
B.Tech - Electronics And Communications Engineering
RGUKT IIIT
Nuzvid04-2023
Skills
- UVM
- SystemVerilog
- Verification IP development
- Python
- AMBA Protocols
Tools
- VCS, Verdi, Protocol analyzer, Cursor, GVIM, Euclide, UNIX
Accomplishments
Bagged Iron Award for autonomous rag picker in InnovateFPGA competition held by INTEL and TERASIC.
Certification
Arm Technical Training Certificate - Introduction to AMBA CHI
Timeline
R&D Engineer, Verification IP
Synopsys
08.2023 - Current
R&D Intern, Verification IP
Synopsys
08.2022 - 07.2023
B.Tech - Electronics And Communications Engineering
RGUKT IIIT