Chilamakuri Sailaja
Bengaluru
Summary
6+ Years of experience as a physical design engineer, with a proven history of delivering high quality designs on time . Expertise in ASIC design, SoC integration, and power optimization techniques ensures timely delivery of complex projects. Adept at problem-solving and critical thinking, fostering effective teamwork to drive project success. Committed to continuous learning and improvement within fast-paced environments.
Overview
7
7
years of professional experience
Work History
Physical Design Engineer
Adroitec Systems Pvt Ltd
Bengaluru
03.2018 - Current
Physical Design Engineer
GOOGLE:
04.2022 - 11.2024
- Responsible for leading the team for five blocks from RTL2GDS II Closer.
- Netlist checks and SDC sanity checks.
- Worked on different experiments in area-wise, macros, and voltage area placement changes.
- Placement: Initial Congestion Analysis, Timing Quality Checks.
- Routability analysis and addressing routing DRCs and LVS issues.
- Post-Route Timing Closure (using PrimeTime)
- All the designs are on-off power-gated, and handling AON-logic clustering was a challenge.
- Faced TCIC issues with IO pad placement, with disjoint power domain creation, and special care has been taken for custom IPs.
- Implemented multiple floorplan experiments as per feedback from the EMIR team and SOC team to arrive at the best floor plan.
- Executed iterative floorplan experiments to resolve row cut issues, LUP violations, IR issues, and Tap & Boundary cell misalignment issues from the CAD flow side.
- Faced secondary PG routing issues due to a lack of secondary power supplies.
- Handled high congestion issues with more Muxes connectivity between power domain crossings.
- Implemented various place experiments to get better results in terms of IR and power recovery.
- Resolved UPF issues that are causing max fanout issues during power domain crossings.
- Handled clock experiments to achieve better clock latencies and to resolve skew issues for clock balancing.
- Resolved the criticality of Base DRCs due to density and latch-up issues, OffGrid, and metal DRCs with Innovus violations based on TCL scripts to clean up bulk violations.
- Resolving LUP density violations was a challenge on the PV side. I faced challenges in floor plan issues with CAD flow and DRC cleanup.
- Mitigated low power cell issues through effective eco solutions.
- Addressed Logical Equivalence Check (LEC) nonequivalent cleanup.
- Performed timing closure analysis, optimization and verification of chip designs.
- Analyzed design data to ensure efficient implementation of complex designs.
- Utilized scripting languages such as Tcl and Tk, Perl, Python to automate the flow of tasks in the physical design process.
- Resolved block level integration problems such as clock tree syntheses issues, signal integrity issues.
- Worked on functional ecosystems and resolved all sign-off issues (LEC/VCLP).
Physical Design Engineer
INTEL
03.2018 - 03.2022
- Contributed to the successful tape-outs of 5 nm, 7 nm, and 10 nm technology nodes.
- Worked on multi-voltage domain block-level tiles.
- Performed critical engineering change orders (ECOs), setup/hold conflict timing paths, and quality fixes for block level.
- Executed formal verification of the customer's initial netlist versus the route netlist.
- Explored multiple floorplans, placement options, and ICC techniques (i.e., setting special routing rules, route guide, route blockages, pre-route of critical nets, including search and repair loop to improve a substantial number of shorts in the design) to solve congestion and routability.
- Place and route of an overly complex timing control circuit with over one hundred system clocks, critical to chip performance, and developed strategies to ensure the design met timing constraints and correlated with engineering specifications.
- Expertise in clock tree synthesis, routing.
- Worked with the full chip timing owner in identifying the optimal solution for hold buffer minimization (for cross-clock hold paths exposed by design) through clock tree tuning and optimization.
- Extensive use of timing-closure techniques, like incremental optimization, path groups, placement blockages, logic bounds, keep-out margin, and cell density control options.
- Validate and troubleshoot the circuitry functionality by running layout versus schematic, and design rule check verifications with Calibre, in accordance with the fabrication procedures. Expertise in manual routing for critical nets/macro pins in the designs.
- Hands-on experience in clock building with DOP.
- Cleaned base level and metal level DRC's using ICC2 and Calibre.
- Worked on full chip Caliber structure.
- Worked on sign-off tools like PT, LEC, and Calibre.
Education
Bachelor of Technology (B.Tech) - Electronics and Communication Engineering
JNT University
AnantapurSkills
- RTL to GDS Expertise
- Exposure to all stages of Physical design such as Floor planning, Placement, CTS, Routing and Timing closure
- Experience in Multi/Single voltage Domain Designs
- Proficient in floor planning with high macro count and resolving congestion issues at Place & Proficient in achieving skew targets and resolving DRC,LVS related issues
- Ability to work on multiple blocks at a time
- Proficient in analyzing timing reports and fixing timing issues ,solving signal integrity issues like EM, crosstalk and antenna effect
- Worked in LEC ,VCLP issues in block level implementation
- STA and timing constraints validation
- Technical Leadership Expertise
- Experience in custom analog IC physical design
- Proficient knowledge in TCL scripting language
Certifications/trainings
PG-Diploma in VLSI Physical Design, Institute of Qsocs PVT ltd., Bengaluru, 05/01/17, 01/31/18
TECHNICAL SKILLS LANGUAGES
TCL | AWK | SED | PERL | C language
TOOLS
Fusion Compiler | ICC/ICC2 | Calibre LVS/DRC | Prime-Time
Timeline
Physical Design Engineer
GOOGLE:
04.2022 - 11.2024
Physical Design Engineer
Adroitec Systems Pvt Ltd
03.2018 - Current
Physical Design Engineer
INTEL
03.2018 - 03.2022
Bachelor of Technology (B.Tech) - Electronics and Communication Engineering
JNT University
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