DEEPAK CHEKURI
BENGALURU
Summary
Passionate SoC Design and integration engineer with 2+ years of experience in successfully developing and debugging FPGA prototype flow for different target FPGA Solutions (HAPS100 and HUINS) and testing boot flow sequence, along with NoC-based interconnect design and RTL design and owning SoC quality checks for SSD memory Controllers. Proficient in enhancing flow efficiency with automation and adept at collaborating with cross-functional teams, ensuring design correctness.
Overview
3
3
years of professional experience
Work History
Sr.Engineer
Samsung Semiconductor India Research
Bengaluru
07.2022 - Current
- Developed and successfully implemented FPGA prototyping setup targeting Xilinx Virtex-Ultrascale FPGA for SATA-based SSD memory controller.
- Established Protocompiler-based FPGA flow for HAPS100 prototyping solution for SSD memory controller.
- Collaborated with multiple teams, both within and outside of the organization, for debugging the FPGA hardware.
- Successfully tested the boot sequence for Xilinx Ultrascale-based FPGA solution and HAPS100 prototyping solution for multiple projects.
- Conducted SoC quality check audits for multiple projects.
- Developed microarchitecture and integration documents for SoC subsystem (BUS interconnect).
- Successfully completed on-site Network on Chip-based interconnect design and RTL generation using ARTERIS FLEXNOC software at South Korea, for SSD Controllers, collaborating with global teams.
- Successfully completed on-site activity in reducing the LUT utilization for Ultrascale-based FPGA and improved the routing congestion at the South Korea Office.
- Hands-on experience on SoC quality checks, i.e., Lint, CDC, and STA.
- Streamlined workflows by automating the processes, enhancing team efficiency.
Internship
Samsung Semiconductor India Research
Bengaluru
01.2022 - 06.2022
- Successfully developed Python tool for integrating SoC subsystems.
- Automated SoC quality tool flow, reducing the time dependency between Synthesis and LEC tools with Make and shell scripts.
Education
M.E.(Embedded Systems)
Birla Institute of Technology And Science
Hyderabad09-2022
B.E.(Electronics And Communications)
College of Engineering, Osmania University
Hyderabad09-2020
Skills
- Tools Used: Synplify-premier, Vivado, Protocompiler, Protocompiler100_runtime, Design Compiler, Primetime, spyglass lint, Meridian CDC, Verdi, Xcelium, Simvision
- Languages : Verilog-HDL, Python, C, tcl scripting, Shell scripting, Make flow
- Methodologies: FPGA Design and Implementation flow, SoC-Integration, Timing Analysis, Clock Domain Crossing (CDC), RTL-to-GDS, JIRA workflow
Timeline
Sr.Engineer
Samsung Semiconductor India Research
07.2022 - Current
Internship
Samsung Semiconductor India Research
01.2022 - 06.2022
M.E.(Embedded Systems)
Birla Institute of Technology And Science
B.E.(Electronics And Communications)
College of Engineering, Osmania University
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