D Sweta Patro
Bangalore
Summary
Verification Engineer with over 2.6 years at Rockwell Automation, excelling in functional and formal verification. Proficient in UVM methodology and Verilog, I am successfully executing complex Ethernet verification projects. A collaborative team player, I thrive in fast-paced environments, driving quality and innovation in every project.
Overview
4
4
years of professional experience
1
1
Certification
Work History
Verification Engineer 1
Rockwell Automation
Bangalore
10.2022 - Current
Gained 2 years and 7 months of expertise in verification engineering at Rockwell Automation.
Technical highlights are mentioned below.
- I worked on multiple unit-level formal and functional verification projects, where I did the test planning, assertions and constraints writing, UVM environment formation, test case execution, code and functional coverage, and regression testing.
- Currently executing functional verification of Ethernet Switch VIP, gaining expertise in protocols such as PRP, SIL2, IPv4, IPv6, and various 802.3 Ethernet frame types, etc.
Advanced VLSI Design and Verification Trainee
Maven Silicon
Bangalore
11.2021 - 09.2022
- Completed training and internship in Advanced VLSI design and verification at Maven Silicon, focusing on projects such as
1. 1x3 Router. Verify the Verilog based design 1x3 router with the help of UVM methodology based testbench environment.
2.. Along with this project also worked on protocols like APB, UART etc.
- Provided guidance and support to trainees on Verilog, leveraging experience as a Design Engineer intern.
Education
Bachelor of Technology - Electrical And Electronics Engineering
National Institue of Science And Technology
Berhampur05-2021
Higher Secondary Examination - Science
SBR Women's Govt. College
Berhampur04-2016
Secondary Examination -
SSVM, Gajapati Nagar
Berhampur04-2014
Skills
- Functional verification
- Formal verification
- Ethernet based verification
- UVM methodology
- Verilog
- SystemVerilog assertions
- Linux
Tools Knowledge
- VCS
- VC Formal
- Xcelium
- IMC
- JasperGold
- Questa Formal
- DVT
- Vivado
- Questasim
Projects
- Maven Silicon - 2022
Router 1x3 (Design and Verification) The router accepts data packets on a single 8-bit port and routes them to one of the three output channels: channel 0, channel 1, and channel 2 Architected the block-level structure for the design using Verilog HDL, and architected the class-based verification environment using UVM-based methodology
Languages
Odia
First Language
Hindi
Proficient (C2)
C2
English
Proficient (C2)
C2
Extra Curricular
- VC of Toastmasters International Club
- Engagement Commitee Member
Certification
Currently doing Synopsys Purple Certification
Hobbies
- Travelling
- Sports
- Photography
Declaration
I hereby declare that the information given above is correct to the best of my knowledge and belief
Date: 17/05/2025 D Sweta Patro
Place: Bangalore
Timeline
Verification Engineer 1
Rockwell Automation
10.2022 - Current
Advanced VLSI Design and Verification Trainee
Maven Silicon
11.2021 - 09.2022
Bachelor of Technology - Electrical And Electronics Engineering
National Institue of Science And Technology
Higher Secondary Examination - Science
SBR Women's Govt. College
Secondary Examination -
SSVM, Gajapati Nagar
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