Kavita Kumari

#2106, Sec-71, Mohali

Summary

Intend to build a career by joining a dynamic team of committed and passionate professionals as a VLSI Design Engineer which will provide a platform where I can utilize my skill set and can help the organization grow.

Education

M. Tech -

Punjab Engineering College

Chandigarh

2024

B.Tech -

Dr. B.R. Ambedkar National Institute of Technology

Jalandhar

06.2017

XII -

Krishna Vidya Mandir

Sikar

2013

X -

Rakesh Academy Sr. Sec. School

Pilani

2011

Skills

CMOS VLSI Design
Static Timing Analysis
Digital Circuits
Verilog HDL

C
Xilinx ISE
Cadence Virtuoso

Projects

UART implementation using Verilog HDL

Designed UART system using shift registers , FSM, parity generator and checker, Baud rate generator, mux etc.
Written the RTL code using Verilog HDL on Xilinx ISE and verified it's functionality by writing test bench.

Asynchronous FIFO implementation using Verilog HDL

Designed asynchronous FIFO memory using memory , write pointer logic, read pointer logic, synchronizer, gray counter etc.
Written the RTL code using Verilog HDL on Xilinx ISE and verified it's functionality by writing test bench.

8-bit ALU implementation using Verilog HDL

Designed 8-bit ALU with arithmetic, logical and shift operations using Verilog HDL on Xilinx ISE and verified it's functionality by writing test bench.

Accomplishments

Secured AIR 538 In GATE 2022
Awarded by “GARGI PURUSHKAR” by Balika Shiksha Foundation Rajasthan, Jaipur for three times for excellent performance in class 8th(93.11%,RBSE) ,10th (94.33%,RBSE) and in 12th(RBSE,91.89% ).

Hobbies

Gardening.
Listening to music

Timeline