Summary
Overview
Work History
Education
Skills
Accomplishments
Projects
Publications
Languages
Timeline
Generic
Krishanvant Singh

Krishanvant Singh

Bangalore

Summary

Dynamic AMS Layout Design Engineer with expertise in Synopsys Custom Compiler and ICV coding, adept at optimizing layouts for advanced technology nodes at Synopsys India. Proven ability to collaborate effectively with circuit design teams, enhancing performance and achieving superior PPA. Committed to delivering high-quality results in fast-paced environments.

Overview

6
6
years of professional experience

Work History

AMS Layout Design Engineer

Synopsys India Pvt. Ltd.
Bangalore
06.2022 - Current
  • Worked on multiple foundry nodes: Intel Process (5 nm), TSMC Process (4 nm, 3 nm, 2 nm), Samsung Process (8 nm, 4 nm).
  • Developed a layout for a variety of cells, which includes combinational and sequential cells with varying drive strength.
  • Involved in area optimizations, routing, and placement of devices for different kinds of layouts such as Multi-Bit Flip-Flop (MBFF), POK cells, DCAP cells, and filler cells.
  • Fixed cells for EM and DFM with PDK change.

Roles and Responsibilities.

  • Involved in the release process for the various tech nodes.
  • Close interaction with the circuit design team is necessary to achieve the best-optimized layout for better PPA.
  • Developed various ICV codes to enhance layout performance.

RTL Design Engineer

Mirafra Technologies (Client - Qualcomm)
07.2021 - 06.2022
  • Worked on 4ff tech node project
  • RTL generation (PLDRC/Compile clean) for TLMM/Padring
  • Run CLP/Pie at padring level
  • Reviewing of CDC/PLDRC violation reported at TLMM/Padring level

Technical Intern

NXP Semiconductors
Noida
07.2019 - 06.2020
  • Reset Domain Crossing, Clock Domain Crossing and Lint sign-off.

Education

M.Tech - VLSI Design

Thapar University
Patiala
06.2020

B.Tech - ECE

Rajasthan Technical University
Kota
06.2016

HSC -

DAV Public School
Jaipur

SSC -

DAV Public School
Jaipur

Skills

  • Synopsys Custom Compiler
  • Xilinx Vivado
  • ICV coding

Accomplishments

  • Awards in Synopsys: Recognized for most optimized Multibit Flops.
  • UGC-NET Qualified

Projects

Design of Low-Power High-Speed Truncation-Error-Tolerant Adder in Digital Signal Processing, Arithmetic circuits are not always required to be accurate in all applications. Compromising with accuracy can increase the speed of the system and also decrease the power consumption. Worked towards this new approach of compromising with accuracy in arithmetic circuits. Design of Self Deterministic Level Shifter, Self Deterministic behaviour signifies that when input is not there or any garbage signal, level shifter determines a unique output value instead of being random in nature as opposed to the random nature of input.

Publications

Recent Progress in Flexible Electronic Display, International Journal of Engineering Trend and Technology

Languages

  • English
  • Hindi

Timeline

AMS Layout Design Engineer

Synopsys India Pvt. Ltd.
06.2022 - Current

RTL Design Engineer

Mirafra Technologies (Client - Qualcomm)
07.2021 - 06.2022

Technical Intern

NXP Semiconductors
07.2019 - 06.2020

M.Tech - VLSI Design

Thapar University

B.Tech - ECE

Rajasthan Technical University

HSC -

DAV Public School

SSC -

DAV Public School

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