Kuntal Sarkar
Kolkata
Summary
Dynamic Graphics Hardware Engineer with a proven track record at Intel Corporation, excelling in GPU validation and IP integration. Expert in Verilog HDL and digital circuit design, I effectively collaborated with cross-functional teams to enhance project outcomes. Known for my analytical skills and innovative problem-solving, I drive successful architectural integration and verification and have a basic knowledge about STA with little hands on Fusion compiler and Prime time
Overview
4
4
years of professional experience
Work History
Graphics Hardware Engineer
Intel Corporation
06.2022 - Current
- Lead IP integration and GPU IP validation efforts across multiple projects, from architectural model setup to physical design integration for the Nova Lake Project.
- Executed IP integration from scratch, translating architectural designs into physical models in alignment with backend floorplans, utilizing Optimus and Intel-specific tools.
- Proficient in Full Chip Activity and Checker tools, addressing DC link, LIRA, HIPs, and memory-related linking issues.
- Conducted Front-End checks (lint, SpyGlass, elaboration, synthesis checks) on IP functional units.
- Collaborated extensively with design and physical design teams to streamline project development.
Formal Verification Intern
Intel Corporation
08.2021 - 05.2022
- Performed IP security verification for Intel server processors using JasperGold, with a focus on cache coherence through IDI BFM.
- Gained expertise in CPU architecture, core tile, and Caching and Home Agent (CA) components.
- Developed tests and validations for UBox and WhoAmI register functionality, including push/pop tests.
Education
Master of Technology - VLSI Design
Vellore Institute of Technology
01.2022
Bachelor of Technology - Electronics and Communication Engineering
Institute of Engineering & Management
01.2018
Skills
- Verilog HDL
- System Verilog
- Optimus
- Xilinx ISE
- Cadence Virtuoso
- LT Spice
- Verdi
- Digital IC Design
- CMOS Design
- Digital circuit design
- GPU validation
- IP integration
- Full chip checks
- Fusion compiler
- Prime time
- STA basics
Training
South Eastern Railways, Kolkata, 07/01/16, Study of Indian Railways Signaling, using Axle Counters & Track Circuit
Languages
- English
- Hindi
- Bengali
Projects
Serial Implementation of PRESENT Architecture, Implemented a lightweight block cipher for data protection using p-box and s-box. Memristor-Based Content Addressable Memory, Designed and implemented efficient CAM memory cells with multilevel storage in Cadence Virtuoso (180nm technology).
Personal Details
- Date of Birth: 08/11/95
- Marital Status: Single
Languages
English
Advanced
C1
Hindi
Advanced
C1
Bengali
Proficient
C2
Timeline
Graphics Hardware Engineer
Intel Corporation
06.2022 - Current
Formal Verification Intern
Intel Corporation
08.2021 - 05.2022
Master of Technology - VLSI Design
Vellore Institute of Technology
Bachelor of Technology - Electronics and Communication Engineering
Institute of Engineering & Management