Linto Thomas
Bangalore
Summary
9.5 years experience in hardware industry spread across RTL design(Automated RTL design, clock domain crossing and sanity Lint,CDC) and post silicon validation (board design, validation of high speed IPs, Automations). Also experienced in leading teams of 3-4 members. Proven ability in improving efficiency in the flow by identifying and automating repeated processes.
Overview
10
10
years of professional experience
Work History
Lead RTL Design Engineer
Cadence Design Systems
Bengaluru
12.2023 - Current
- As part of UCle PHY IP team, added APB automotive features to the IP with minimum additional pins while having all the debug and fault logging features
- Developed end to end automation for RTL design which is clean from Sanity, Lint and CDC
- Collaborated with verification, PD and validation teams for finding issues and root cause
- Built features in RTL design which involves clock domain crossing and focus on low power
- Enabled shell based automation of Lint/CDC and sanity before it is released to customer
Lead Post Silicon Validation Engineer
Cadence Design Systems
Bengaluru
06.2015 - 12.2023
- Led a team of 3-4 freshers in highly critical first ever tapped out analog front end projects and completed with numerous challenges
- Validated multiple IPs with high speed instruments along with HTOL, ESD and high quality documentation of the detailed work for customer
- Worked in multiple board design of varying complexity along with layout teams and vendors for enabling all the test features
- FPGA design and lab debug experience
Education
Master Of Technology - Embedded System Design
Birla Institute of Technology
06.2023
Bachelor of Technology - Electronics And Communication
College of Engineering
TrivandrumSkills
- Python
- Visual Basic
- Shell Automations
- Automated RTL Generation
- System Verilog
- IPXACT-2014
- Team Leadership
- Collaboration
Accomplishments
Quarterly Champion, 12/01/23
For leading highly acclaimed challenging project while meeting all milestones
Languages
English, Hindi, Malayalam
Timeline
Lead RTL Design Engineer
Cadence Design Systems
12.2023 - Current
Lead Post Silicon Validation Engineer
Cadence Design Systems
06.2015 - 12.2023
Master Of Technology - Embedded System Design
Birla Institute of Technology
Bachelor of Technology - Electronics And Communication
College of Engineering