Navaneeth S Shetty

Master’s student in Microelectronics and VLSI Technology with hands-on experience in physical verification using Calibre tools(Siemens EDA). Worked on advanced-node semiconductor designs focusing on ESD protection path analysis and reliability verification for full-chip tape-outs. Strong foundation in CMOS device physics and semiconductor reliability with interest in ESD/latch-up protection design.

Connectivity-Aware Placement and Floorplanning Algorithm

• Developed a connectivity-driven placement algorithm using k-connected clustering techniques to optimize interconnect wirelength in SoC layouts.
• Improved placement quality by increasing core area by 20%, reducing routing congestion, parasitic capacitance, and interconnect-related power consumption.

Design of an Approximate Multiplier

• Designed and implemented an approximate multiplier architecture optimized for reduced power consumption and silicon area with controlled computational accuracy trade-offs.
• Evaluated architectural trade-offs for error-tolerant applications including image processing and machine learning accelerators.

• Maven Silicon – Physical Design Fundamentals (2023)
  Cadence – RTL to GDS Physical Design Flow (2024)
  STMicroelectronics – Calibre Basics (2025)