NIKHILA PRANAVI ADARI

Responsibilities:

As a senior verification engineer, took complete ownership of formal verification and a security sub system verification.

Key contributions:

• Worked on various Cadence formal applications, to increase quality of verification and to catch bugs on early project cycle.
• Simplified an existing formal workflow in our project environment.
• Regression cleanup, debug and coverage analysis for a security subsystem.
• Added new test scenarios to thoroughly verify the RTL updates.
• Automation of glitch checker implementation at various interface boundaries to catch any glitches present during GLS simulations using shell.
• Worked closely with the cross-functional teams in case of any support required.

For 11 months I worked as a verification engineer intern, during which I learnt system Verilog, UVM and on creating a testbench architecture for UBUS and APB protocols in UVM.

5 months of Internship where I worked on downlink of U- plane in ORAN protocol implementation.