Summary
Overview
Work History
Education
Skills
Extracurricular Activities
Disclaimer
Timeline
Generic
PAILA KANAKA MAHALAKSHMI

PAILA KANAKA MAHALAKSHMI

Golugonda

Summary

Dynamic Physical Design Trainee with hands-on experience at a leading semiconductor firm, excelling in timing closure and place and route optimization. Proficient in Cadence tools and scripting languages, I developed strategies that enhanced chip performance and power efficiency, while effectively collaborating with cross-functional teams to meet tight deadlines.

Overview

1
1
year of professional experience

Work History

Physical Design

Trainee
Hyderabad
08.2024 - Current
  • Ensured proper integration between RTL code and backend flows like synthesis and P&R flow.
  • Generated reports to analyze design metrics such as total wirelengths, number of vias.
  • Ran ECOs on existing designs using scripting languages like TCL or Perl.
  • Executed block level Place and Route tasks under tight time frames while meeting quality goals.
  • Utilized Cadence tools for timing closure, clock tree synthesis, signal integrity analysis, placement and routing optimization.
  • Documented best practices related to physical design methodology used throughout projects.
  • Developed physical design strategies to optimize chip performance and power consumption.
  • Utilized scripting languages such as Tcl and Tk to automate the flow of tasks in the physical design process.
  • Evaluated and verified physical design requirements to ensure accuracy and completeness.
  • Conducted physical design activities such as floor planning, synthesis, timing closure, power analysis and STA.

Education

B.Tech - Electrical and Electronics Engineering

Avanthi Institute of Engineering And Technology
Tamaram, Andhra Pradesh
05-2024

Diploma - Electrical and Electronics Engineering

Avanthi Institute of Engineering And Technology
Tamaram, Andhra Pradesh
04-2021

10th - SSC

ST. Ann's English Medium High School
KDPeta, Andhra Pradesh
03-2018

Skills

  • Scripting languages
  • Timing closure
  • Floorplanning
  • Cadence tools
  • Place and route
  • Clock tree synthesis
  • Static timing analysis
  • Design rule checking

Extracurricular Activities

Participated in NATIONAL SERVICE SCHEME (NSS) programs

Disclaimer

I do hereby declare that the information mentioned above is true and complete to the best of my knowledge and belief.

Timeline

Physical Design

Trainee
08.2024 - Current

B.Tech - Electrical and Electronics Engineering

Avanthi Institute of Engineering And Technology

Diploma - Electrical and Electronics Engineering

Avanthi Institute of Engineering And Technology

10th - SSC

ST. Ann's English Medium High School
PAILA KANAKA MAHALAKSHMI