Pavan Jamendar Muvvala
Bengaluru
Summary
Physical Design Engineer with 7+ years of experience in advanced nodes (7nm, 5nm, 4nm, 3nm), successfully contributing to 10+ tapeouts across high-performance SoCs for clients like INTEL, NVIDIA, Google and Media Tek. Expertise in timing closure, congestion optimization, EMIR analysis, and full-chip/block-level signoff. Strong experience in debugging complex timing and physical design issues across multiple corners. Currently leading block-level signoff and collaborating with cross-functional teams for timing and power closure.
Overview
10
10
years of professional experience
Work History
Senior Engineer
LeadSoc Technologies Pvt Ltd
Bengaluru
05.2024 - Current
- Led block-level physical design from RTL to GDSII for MediaTek SoCs, contributing to 3 successful tapeouts
- Achieved timing closure by fixing setup/hold violations across multiple corners
- Debugged cross-domain timing issues and coordinated SDC/RTL fixes
- Improved timing QoR through placement, buffering, and CTS optimizations
- Owned physical and power signoff by resolving DRC/LVS and EMIR violations
- Leading a team of 3 engineers and ensured timely project delivery
Design Engineer II
Wafer Space Semiconductor Technologies Private Limited
Bengaluru
03.2022 - 05.2024
- Owned block-level signoff (timing, PV, EMIR) for 3nm/4nm designs for the client Google , delivering 3 successful tapeouts
- Analyzed and resolved IR drop, EM violations, and power integrity issues
- Optimized floorplan to reduce congestion hotspots and improve routing efficiency
- Debugged corner-case timing violations and implemented placement blockages
- Collaborated with frontend/STA teams to drive SDC and RTL fixes for timing closure
Physical Design Engineer-1
Centaurs semiconductors
Bengaluru
05.2019 - 03.2022
- Worked on physical design of advanced nodes (7nm/5nm) for Tier-1 clients including Intel and NVIDIA, contributing to 3 tapeouts at Intel and 1 tapeout at NVIDIA
- Handled multiple blocks per project (up to 3 blocks at Intel and 2 blocks at NVIDIA), driving block-level closure from floorplan to signoff
- Achieved timing closure by fixing setup/hold violations, including manual ECO generation and critical path optimization
- Performed floorplan iterations and resolved congestion hotspots, improving routability and overall QoR
- Improved clock QoR by optimizing CTS and resolving skew and latency issues
- Debugged timing issues across synthesis and placement stages, enhancing design performance and stability
Physical Design Trainee
Semicon Techno Labs
Bengaluru
05.2018 - 05.2019
- Executed physical design engineering at 28 nm technology level.
- Conducted floor planning based on fly line analysis to optimize layout.
- Managed PNR flow, including floor planning, placement, CTS, and routing tasks.
- Performed congestion analysis during placement and resolved issues using partial blockages.
- Implemented ECOs to achieve timing closure and enhance performance.
- Addressed DRC and LVS issues to ensure design compliance.
Sr. Bench Sales Recruiter
Isolve Technology
Hyderabad
12.2015 - 06.2018
Education
Master of Technology - VLSI Design
Lovely Professional University (LPU)
Punjab01-2016
Skills
- Tools:
ICC2, Innovus, PrimeTime, Tempus, Calibre, StarRC, RedHawk - Technical Skills:
Physical Design (Floorplan, Placement, CTS, Routing)
Timing Closure & STA
EMIR Analysis
Physical Verification (DRC/LVS)
- Scripting:
Tcl (basic )
Timeline
Senior Engineer
LeadSoc Technologies Pvt Ltd
05.2024 - Current
Design Engineer II
Wafer Space Semiconductor Technologies Private Limited
03.2022 - 05.2024
Physical Design Engineer-1
Centaurs semiconductors
05.2019 - 03.2022
Physical Design Trainee
Semicon Techno Labs
05.2018 - 05.2019
Sr. Bench Sales Recruiter
Isolve Technology
12.2015 - 06.2018
Master of Technology - VLSI Design
Lovely Professional University (LPU)