HEMANTH VARMA PUTTA

Project Name: JBI

Technology Nodes: 28nm

Role: Synthesis, LEC and STA Analyzation of the block

Responsibilities:

• Worked on Synthesis and Optimizing a block and on Clock Gating adding ICG's if the clock needs to be gated.
• Performed LEC check and tried to enhance and implement the corrections required using ECO.
• Performed Scan insertion to add scan flops to test the flops during DFT.
• Performed low power synthesis and VCLP checks on the synthesis netlists.
• Debugged the issues such as wrong placement of the low power cells and missing cells such as level shifters.
• Analyzing all Timing Paths(IN2REG,REG2REG, REG2OUT,IN2OUT).
• Analyzing MCP paths for setup and hold. ICG analyzing the timing paths and its application.
• Debugging issues such as max_cap ,max_tran, setup, hold and crosstalk.

Tools Used: dc_shell(synthesis), fm_shell(LEC), VCLP (vc_static_shell), ICC2_shell, Pt_shell

Technology Nodes: 4nm

Responsibilities:

• Worked on performing STA runs at the different stages of Physical design flow such as synthesis, PCO and PRO using Dragon flow and flow tracer.
• Analyzing the reports of the STA runs and debugging the issue caused the setup and hold violations.
• Worked on performing ECO's, Tweaker of hold eco's and Tempus setup eco's for fixing setup and hold.
• Analyzing the eco reports and debugging the fix rate and finding whether most of the violated paths are fixed or not and if not, debugging the issues for low fix rate.

Tool Used: TEMPUS

• Project: Wild Cat Lake
  Technology Nodes: 1.8nm
  Location: Bangalore
  Responsibilities:
• Performed DRC/LV clean up from scratch (base layers to top metal layers) with ICV validator.
• Handled complex blocks and analyzed blocks from base layers to top metals for better cell placement in congestion regions.
• Performed drc clean up with minimum iterations.
  Implemented ECOs (Buffers and Size cells) to meet timing in blocks.
• Performed re-routings and cell movements in routing congestion regions to reduce the shorts and drc violations.
• Performed the various FM violations fixes in antenna.
• Performed Metal patterning’s for metal pattern violations near macros and in core area.
  Tool Used: ICV - Validator