Summary
Overview
Work History
Education
Skills
Timeline
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Valluri Murali Manohar

BANGALORE

Summary

Accomplished Engineer with 2.5 years of expertise in Synthesis,Physical Design/STA, honed at CAPGEMINI and MIRAFRA, serving prestigious clients like QUALCOMM. Excelled in optimizing complex designs for 4nm and 28nm technology nodes, demonstrating strong analytical skills and a knack for innovative problem-solving. Proven ability in enhancing design efficiency and achieving timing closure, underscored by TCL scripting.

Overview

2025
2025
years of professional experience

Work History

ASSOCIATE I - ENGINEER

CAPGEMINI
08.2022 - Current
  • Worked on Synthesis and Optimizing a block and on Clock Gating adding ICG's if the clock needs to be gated
  • Performed LEC check and tried to enhance and implement the corrections required using ECO
  • Performed Scan insertion to add scan flops to test the flops during DFT
  • Worked on creating different power domains of different voltages, creating isolation and level shifter logics where to be placed and creating power ports and nets for power domains
  • Performed low power synthesis and VCLP checks on the synthesis netlist
  • Debugged the issues such as wrong placement of the low power cells and missing cells such as level shifters
  • Performed Physical design flow(Data preparation, Floorplan, Power plan, Placement, Routing and STA/Timing closure)
  • Analyzing all Timing Paths(IN2REG,REG2REG, REG2OUT,IN2OUT)
  • Analyzing MCP paths for setup and hold
  • ICG analyzing the timing paths and its application
  • Debugging issues such as max_cap ,max_tran, setup, hold and crosstalk
  • Client: Chipedge PVT ltd
  • Project: JBI
  • Location: BANGALORE
  • Duration: 9 months (March - November 2023)
  • Technology Nodes: 28nm
  • Role: Synthesis, LEC and STA Analyzation of the block
  • TOOL USED: dc_shell(synthesis), fm_shell(LEC), VCLP (vc_static_shell), ICC2_shell, Pt_shell

STA

CAPGEMINI
  • Worked on performing STA runs at the different stages of Physical design flow such as synthesis, PCO and PRO using Dragon flow and flow tracer
  • Analyzing the reports of the STA runs and debugging the issue caused the setup and hold violations
  • Worked on performing ECO's, Tweaker of hold eco's and Tempus setup eco's for fixing setup and hold
  • Analyzing the eco reports and debugging the fix rate and finding whether most of the violated paths are fixed or not and if not, debugging the issues for low fix rate
  • Client: QUALCOMM
  • Location: BANGALORE
  • Technology Nodes: 4nm
  • TOOLS USED: TEMPUS

Physical Design Engineer II

MIRAFRA Technologies
  • Generated timing ECO's.
  • Debugged the constrains issues and given the feedback to constraint team.
  • Analysed the timing reports and given feedback to the block owner.
  • Debugged DYNAMIC and STATIC IRDROP
    Analyzed instance placement relative to power domains and power bumps to identify resistance issues.
  • Inspected missing vias and grid/metal connections ensure to minimize resistance
    Debugging the Unconnects.
  • Analyzed instance to find the reasons that causing the unconnects in primary and secondary power domains.
  • Worked on python scripting to extract the instance from a dvd file which having the irdrop more than 10% and finding the worst 10 paths in TEMPUS and getting all the instances from all the worst paths.
  • Client: QUALCOMM
  • Location: BANGALORE
  • Technology Nodes: 4nm
  • TOOLS USED: RHSC,Primetime

Education

M.TECH - VLSI DESIGN

GITAM
VISAKHAPATNAM
01.2022

B.TECH - ELECTRONICS AND COMMUNICATION ENGINEERING

01.2020

Skills

  • Synthesis
  • Analysing Timing reports
  • Sanity checks
  • STA/Timing Closure
  • LEC (Logic Equivalence Check)
  • TCL
  • PERL
  • Prime Time (PT shell)
  • FM (formality) shell
  • Tempus
  • RHSC
  • DMSA
  • Tweaker

Timeline

ASSOCIATE I - ENGINEER

CAPGEMINI
08.2022 - Current

STA

CAPGEMINI

Physical Design Engineer II

MIRAFRA Technologies

M.TECH - VLSI DESIGN

GITAM

B.TECH - ELECTRONICS AND COMMUNICATION ENGINEERING

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