Prachi Goutam

Enthusiastic VLSI Engineer who stands out through hard work & excellent organization skills. Eager to adapt & utilize my experience, industry standard tools & methodology to deliver high quality solutions for gaining organizational goals as well as enhancing my career in VLSI Domain

IDE TOOLS AND UTILITIES- Cadence XCELIUM & INCISIVE, Cadence Virtuoso, Xilinx ISE Design Suite, Modelsim, Vivado,Questa, FPGA Knowledge, MATLAB, Arduino,mbed online Compiler, Kiel-uVision (8051 & Arm microcontroller),

OPERATING SYSTEM –Windows, Ubuntu (Linux)

UDEMY CERTIFICATION- System Verilog, AMBA AXI, PYNQ FPGA, UVM Methodolgy basics

Smart Dustbin for Differently Abled People from Government of India

[1] SIFIVE SRAM   [ 7 nm technology]

     HDL - Verilog     HDVL - System Verilog      Tool - Cadence INCISVE

    Responsibilities :    Design SRAM memory model and its testbench

                                   Functional verification of memory using DMA and BIST

[2] INTEL MRAM   [22 nm technology]

      HDL - Verilog     HDVL - System Verilog      Tool - Cadence XCELIUM

      Responsibilities:    Designing and Verification of Phased locked loop scan chain 

                                    Gate level Simulation and SDF Timing Checks for different corners

[3] GROQ SRAM [ 5 nm technology]

      HDL - Verilog     HDVL - System Verilog       Tool - Cadence XCELIUM , CONFRML

      Responsibilities :     Design RTL Testchip Code and integration of Glue logic

                                      Linting through HDL Analysis and Lint Tool CADENCE

                                      Design RTL verification code for DMA mode 

                                      Done Gate level & SDF simulation

[4]  BOSTON SCIENTIFIC  [180 nm technology]

       HDL - Verilog    HDVL - System Verilog  Tool - Cadence XCELIUM, VIVADO,FPGA KCU105

       Responsibilities:    Designing BIST block & wrapper & writing testbench to verify it 

                                      Design RTL verification code for BOSTON testchip in DMA mode

                                      After Synthesis done Gate level and SDF simulation

                                      Designing Testcode for BOSTON Testchip for FPGA validation 

[5]  Virtual Processing Unit VPU  [12 nm technology]

       HDL - Verilog     HDVL - System Verilog      Tool - Cadence XCELIUM

        Responsibilities :   Develop & Verify RTL Code for BIST & BISR block of VPU Scratchpad

                                      Designing Verification Code for Subsystem BIST & BISR verification  

                                      Designing Verification code for PCIE BIST & BISR Verification

[6]  GOOGLE     [3 nm technology]

         HDL - Verilog     HDVL - System Verilog       Tool - Cadence XCELIUM

        Responsibilities :   Architect and design memory model in Behavioral model

                                      Design verification code for Functional & Assertion based Verification

[7]   AMBA ( Advanced Microcontroller Bus Architecture)  Protocol   

         HDL -Verilog     HDVL - System Verilog        Tool - Cadence XCELIUM

         Responsibilities :    Develop RTL Code for AHB and APB Protocol 

                                        Design Verification code using System Verilog  

                                        Designing AHB to APB Bridge  and Verification      

[8]   AXI (Advanced Extensible Interface) - AMBA AXI4 Protocol Verification 

          HDVL - Verilog     Methodology -UVM        Tool - Cadence XCELIUM,VIVADO

          Responsibilities :     Design  RTL code and verification of AXI Lite using VIVADO

                                          Architect Class based verification environment using UVM

                                          Verified using single master single slave design 

                                          Generated functional coverage for verification sign off

[9]   Develop Diagnostic Tool for verification and validation of VME

          HDL - Verilog         Tool - Xilinx and Spartan 3 FPGA

         Responsibilities  :   VME is master-slave computer architecture bus and supports asynchronous signalling scheme used in industry and military application .This module will capture transitions and durations of various control signals of the VME bus and verify them as per VME bus guidelines. This  system will also notify about the violations on the bus during the transfer of data and sequence of modules executed and record it and used as memory module

[10]  Router 1x3

          HDL - Verilog         HDVL- System Verilog       Tool - Xilinx Software

         Responsibilities :   Router is a device that forward data packets between computer networks. It drives the incoming packet to an output channel based on the address field content in packet header . RTL Design and Verified for different block to design router .

ACADEMIC PROJECTS

[11] SPI Communication of Two Arduino Boards

[12] FPGA based Ping Pong Game using Spartan-6 (Reference link - https://youtu.be/mv51AlUd8yo) (Major)

[13] Electronic Nose System (Minor)

• Opportunity to work with Scientist in DEFENCE RESEARCH AND DEVELOPMENT ORGANISATION (DRDO HYDERABAD) in Industrial Training on MATLAB GUIDE
• Advanced Digital Design and Verification from MAVEN Bangalore
• Implementation of Digital Filters Using ARM Microcontroller STM32F401RE presentated paper at 8th International Conference on Innovation in Electronics & Communication (ICIECE-2019)
• One Week faculty training program on Robotics and Embedded System organized at IIT Roorkee and Attended Short Term Courses on Analog IC Design Circuit and Layout Design Methodology using Cadence design Flow at Devi Ahilya University (DAVV INDORE

• Received Patent Published & Granted from Government of India for Smart Dustbin for Differently Abled Person
• Class Representative in M.Tech batch and Coordinator of National Conference of IEEE
• BSNL-AICTE(EETP) with GOLD certified engineer gaining EXCELLENCE certificate (2016), SILVER certified engineer, PROFICIECY certificate (2015)
• Selected for central sector scholarship from Higher Secondary Board of School Madhya Pradesh(2012)
• Consolation position in State level Kalidas Samaroh Dance and Drama Competition in Bhopal (2005)
• Actively participated in cultural and technical workshop during academics