Punith R
Bengaluru
Summary
Accomplished Senior ASIC Verification Engineer with a proven track record at Company Name, specializing in SystemVerilog and UVM methodology. Enhanced product quality and reduced verification cycle time by 20% through innovative strategies. Adept at mentoring teams and driving projects to achieve 98% verification coverage, showcasing strong analytical and leadership skills.
Overview
1
1
Certification
Work History
Senior ASIC Verification Engineer
Company Name
- Current
- Verified high-speed coherent interconnect designs, architectures, and golden models
- Developed and executed test plans, test cases, and test benches using SystemVerilog and UVM
- Collaborated with architects, designers, emulation, and silicon verification teams to ensure design correctness
- Implemented verification strategies that reduced the verification cycle time by 20% and enhanced product quality
- Mentored junior engineers and interns in verification methodologies and best practices
- Utilized industry-standard protocols such as PCIE, CXL, and CHI in verification environments
- Analyzed and debugged issues in ASIC/FPGA designs using simulation tools
- Led a team to achieve 98% verification coverage on a complex chip design using UVM
- Developed automated scripts that cut down manual verification time by 40%
- Improved bug detection rate by 15% through enhanced verification methodologies
ASIC Verification Engineer
Company Name
- Current
- Prepared node/network configurations for tests and designed new test cases
- Experienced in Unix and/or Linux environments with proficiency in shell scripting
- Worked on interoperability testing with device vendors and utilized tools like SoapUI and Selenium
- Maintained and updated test documents and environments
- Participated in project meetings to provide feedback on product documentation and limitations
- Reduced time spent on manual verification by implementing automated test scripts
- Contributed to the development of test plans and verification strategies that ensured 100% functional verification coverage
Education
Master's Degree - VLSI Engineering
Manipal University
Udupi,India08-2016
Skills
- SystemVerilog
- Perl
- Python
- UVM Methodology
- AXI, APB, AHB
- CHI
- Functional coverage and assertion-based verification
- Debugging and analytical skills
- Test plan development
- Debugging techniques
- Project coordination
- Performance verification
- Functional coverage
- Code coverage analysis
- Constraint random verification
Certification
- Certificate in ASIC Verification, [Issuing Institution], [Year]
- Certificate in Advanced Verification Methodologies, [Issuing Institution], [Year]
Projects
[Project Name], [Briefly describe the project, focusing on your role and the technologies used.], [Highlight any significant achievements or improvements made during the project.]
Professional Memberships
Member, [Professional Organization], [Year Joined]
Timeline
Senior ASIC Verification Engineer
Company Name
- Current
ASIC Verification Engineer
Company Name
- Current
Master's Degree - VLSI Engineering
Manipal University
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