Summary
Overview
Work History
Education
Skills
Timeline
Languages
Generic
Raval Raj

Raval Raj

Bayad

Summary

  • Electronics Engineer with hands-on experience in RTL design and basic verification using Verilog and SystemVerilog. Good understanding of digital design concepts such as FSM, timing, and flip-flops. Familiar with writing testbenches, performing simulation, and debugging using waveform analysis. Also have exposure to DFT concepts including scan chain and basic fault models. Looking for an entry-level Design Verification or DFT role where I can learn, contribute, and grow in the VLSI domain.

Overview

3
3
years of professional experience

Work History

DFT Intern

eInfochips
Ahmedabad
07.2024 - 08.2025
  • Executed scan insertion at RTL and gate level for multi-clock designs.
  • Implemented muxed-D scan architecture and stitched scan chains.
  • Conducted DFT design rule checks, resolving clock and reset issues.
  • Debugged scan chain connectivity and addressed shift/capture mismatches.
  • Developed SPI controller with integrated DFT implementation.
  • Inserted scan chains, checking full scan connectivity and verified operations.
  • Performed DFT checks, rectifying controllability and observability problems.

Trainee

maven silicon
banglore
05.2022 - 05.2023
  • 1x3 Router – RTL Design and Verification
  • Description:
    Designed a simple 1x3 router which takes 8-bit input data and sends it to one of three output channels based on address.
  • Used FSM to control data routing.
  • Developed SystemVerilog testbench for thorough design verification and validation.
  • Performed simulation using Questasim.
  • Technologies: Verilog, SystemVerilog, UVM, Questasim

Education

M.Tech - VLSI (SD)

GANPAT UNIVERSITY
Mehsana
01-2026

Bachelor of Engineering - Electronics and Communications

GTU-GEC MODASA
Modasa
07-2022

Diploma - Electronics and Communication

Government Polytechnic
Palanpur
08-2018

Skills

  • Scan design methodologies
  • SystemVerilog
  • VLSI design
  • C and C programming
  • Python programming
  • Linux operating system
  • Communication skills

Timeline

DFT Intern

eInfochips
07.2024 - 08.2025

Trainee

maven silicon
05.2022 - 05.2023

M.Tech - VLSI (SD)

GANPAT UNIVERSITY

Bachelor of Engineering - Electronics and Communications

GTU-GEC MODASA

Diploma - Electronics and Communication

Government Polytechnic

Languages

  • Hindi
  • Gujarati
  • English
Raval Raj