To secure a challenging position in an esteemed organization which help me to realize my potential to enhance my skill-set in the field of VLSI Physical Design and help the organization grow.
Overview
8
8
years of professional experience
Work History
InSemi Technology Services Pvt. Ltd
08.2025 - Current
VLSI Training
VLSIGURU
Bangalore
02.2024 - 11.2024
SME
Bartleby Technologies Pvt Ltd
Bangalore
05.2018 - 06.2020
Apprentice
Uttar Pradesh Power Corporation Limited
05.2017 - 04.2018
Education
B. Tech - Electronics Communication Engineering
Dr. A. P. J. Abdul Kalam University
08.2023
HSC - Physics, Chemistry, Math
Uttar Pradesh Board
04.2017
Diploma - Electronics Engineering
Board of Technical Uttar Pradesh (BTEUP)
04.2015
SSC - Science, Hindi, Math
Uttar Pradesh Board
04.2012
Skills
28nm technology nodes
Fusion Compiler
ICC2
PnR flow
Floor plan
Power Plan
Placement
CTS
Routing
Timing fixes
Congestion fixes
Static timing analysis
Physical Verification
TCL scripting
Linux Environment
Digital Circuit design
CMOS concepts
Unix/Linux environment
Windows
Projects
B. Tech Project, Case study report on Fault Analysis in DWDM Technology for TCL-GOOGLE
Languages
English, Pro
Hindi, Pro
Projects Summary
ORCA TOP, 28nm, 20, 600MHz, 700000, ICC2, 6 months, PNR Implementation of block with 700k instance count with 600MHz from Netlist to GDSII., Did initial/sanity checks on the inputs., The block is rectangular in shape and congestion critical., Performed the floor planning by arranging the macros based on the connectivity., Worked on bounds creation & place blockages creation., Tried different CTS strategies to maintain insertion delay and skew within limit., Achieved skew and latency targets through different CTS experiments., Fixed congestion issue by performed different techniques like cell padding and adding blockages., Cleared the setup, hold violations.