Sai Kumar Akula
Chebrole
Summary
Highly-motivated employee with desire to take on new challenges. Strong worth ethic, adaptability and exceptional interpersonal skills. Adept at working effectively unsupervised and quickly mastering new skills.
Overview
3
3
years of professional experience
1
1
Certification
Work History
Advanced ASIC Verification Trainee
Maven Silicon
Banguluru
06.2024 - Current
- Advanced verification in Verilog.
- Verification Methodologies-UVM, Assertion based Verification.
- ASIC Verification Methodologies.
RTL Design Engineer
Capita
Newcastle Upon Tyne
01.2022 - 08.2023
- Developed RTL code for ASIC designs using Verilog and SystemVerilog.
- Implemented designs in Verilog HDL and VHDL languages.
- Designed state machines using Finite State Machines and implemented them into Verilog code.
- Performed simulation-based tests on RTL models using SystemVerilog and UVM based environments.
Project Lead
Northumbria University
Newcastle Upon Tyne
01.2021 - 07.2021
- January 2021 to June 2021, During Master’s degree worked as project lead along with professor on one of the projects related to Visible light Communications (VLC).
Advanced Practice Research Intern
Northumbria University
Newcastle Upon Tyne
01.2021 - 06.2021
- January 2021 to June 2021, worked as intern under university professor on FPGA/Subsystems/Systems development using RTL coding-VHDL/Verilog Languages (Xilinx).
Education
Master of Science - MICRO ELECTRONICS AND COMMUNICATIONS Eng.
Northumbria University
Newcastle Upon Tyne, England- United Kingdom06-2021
Bachelor of Technology - ECE
Sri Vasavi Engineering College
Tadepalligudem, India05-2019
Skills
▪ RTL coding, RTL design flow, Synthesis and Simulation and Test benches
▪ FGPA design flow, FPGA architecture, Synthesis and Simulation, Front-end
▪ HDL coding
▪ Flatform: Xilinx Vivado
▪ VHDL, Verilog and familiar with System Verilog
▪ Familiar Protocols-UART, I2C, SPI, ETHERNET and USB
▪ Python
▪ Matlab Simulink
▪ C programming
Languages
Telugu
First Language
English
Advanced (C1)
C1
Certification
- Certificate of Merit- Received certificate of Merit from Kakinada Institute of Engineering and Technology (KIET) for obtaining excellent academics.
- Design and Analysis of Digital Circuits (VHDL/Verilog)- Obtained certification for completing the course online from Alison.
Timeline
Advanced ASIC Verification Trainee
Maven Silicon
06.2024 - Current
RTL Design Engineer
Capita
01.2022 - 08.2023
Project Lead
Northumbria University
01.2021 - 07.2021
Advanced Practice Research Intern
Northumbria University
01.2021 - 06.2021
Master of Science - MICRO ELECTRONICS AND COMMUNICATIONS Eng.
Northumbria University
Bachelor of Technology - ECE
Sri Vasavi Engineering College
- Certificate of Merit- Received certificate of Merit from Kakinada Institute of Engineering and Technology (KIET) for obtaining excellent academics.
- Design and Analysis of Digital Circuits (VHDL/Verilog)- Obtained certification for completing the course online from Alison.
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