Saurabh Kalambe

Well versed with ASIC design flow (RTL to GDSII). Understanding of inputs and outputs of all the stages involved in physical design flow (APR). Efficient in timing-aware and congestion-driven macro placement during Floor Planning. Power planning with IR drop and EM analysis. Placement of core logic, Clock Tree Synthesis (CTS), Routing, and finding timing exceptions at each stage. Static Timing Analysis (STA): Knowledge in interpreting timing reports, fixing Setup and Hold violations, effects of clock skew on timing, and timing analysis of latches. Identifying and constraining timing paths, analyzing timing under various PVT corners, OCV, False Paths, Half-cycle paths, MCMM, and CRPR. Fair knowledge of Signal Integrity (SI) issues like Crosstalk. Reliability issues like Electromigration and Antenna effect. Hands-on experience with EDA Tools: APR - Synopsys ICC, STA - Synopsys PrimeTime. Analyzing and understanding of Linux shell and TCL.
Aware of different files: Lib, DEF, LEF, SDC, and SPEF. Comprehensive knowledge of VLSI fundamentals, CMOS theory, Network Analysis, and Logic Design.