Shaik Rajeena
Summary
Dedicated Validation Engineer with overall 5 + years of experience in Development, Testing, Analysis, Design ,verification and implementation of various embedded systems software and hardware functionality.
Overview
5
5
years of professional experience
6
6
years of post-secondary education
Work History
Technical staff Engineer
Mirafra Technology Private Limited, Qualcomm
03.2021 - Current
- Strong work experience in Camera IP
- Experience in using defect tracking & Automation tool like JIRA
- Knowledge of MIPI protocol
- Strong work experience in a Web-based graphical interface like GIT HUB
- Having experience on programming language such as C
- Experience in development of Camera related drivers and system tests releases
- Hands on experience on Linux platform & Vim editor
- Experience on T32
- Experience on power activities
- Highly skilled in Test case Development with various cross tools, executing test with developed workflow.
Product Validation Engineer
Micron Technology Operations India LLP
Hyderabad
08.2019 - 03.2021
- Strong work experience in SSD Validation with NVMe protocol
- Experience in using defect tracking & Automation tool like JIRA
- Knowledge of NAND-Technology
- Strong work experience in a Web-based graphical interface like
- GIT HUB
- Having experience on programming languages such as Python Scripting, C
- Highly skilled in Test case Development with various cross tools, executing test with developed workflow.
Post Silicon Validation Engineer
EmWare Technologies (INDIA) Pvt. Ltd
08.2014 - 09.2016
- Experience in Pre & Post Silicon Validation of various ARM based SOC-IP blocks as Power management Unit, SD-Host controller, UART, I2C (8/16/32 -bit)
- Knowledge in Zebu Emulation Platform & FPGA emulation Platform
- Experience in debugging and development tools such as DMM, DSO, debuggers and analysers etc
- Has the ability and experience to understand the architecture and lifecycle of SDLC in depth
- Experience in using defect tracking & Automation tool like JIRA
- Has the ability and experience to understand the architecture and lifecycle of SDLC in depth
Education
M.Tech - Embedded Systems
Annamacharya Institute of Technology And Sciences
09.2016 - 08.2018
B. Tech - ECE
JNTUA
01.2010 - 01.2014
Skills
Programming Peripheralsundefined
Accomplishments
- Helped to debug critical bugs in post silicon validation with the team to fullfill project allignments to meet the CS/ES ETAs
- Fullfilled all the tasks in execution assigned by the team lead.
- Successfully raised all the firmware related bugs to maintain stable firmware in SSDs.
- Got selected for Pratibha award from my institute.
Additional Information
Project Name: Post and Pre silicon Validation on Camera IP of different Qualcomm Application platforms.
Roles & Responsibilities: Need to go through product architecture and product related specs and need to develop test plan.Prepare the testplan for both pre silicon as well as SOD to meet the project timelines.By collaborating with emulation team, Sys performance team, Software team, SPT team to list down the ETAs for releasing camera related drivers and system tests. Execute all functional, power, performance vectors for all the camera blocks. Take the code from legacy internal product if any changes required modify accordingly and for new feature develop the test cases.Identify feature of camera to be validated and interacted actively with architect to freeze the list of features to be validated. Compile the code with proper structure and drivers without any errors . Execute all the test vectors on T32 if any failure occurs debug them by following proper steps.Debug the failures, if necessary, raise the Jira’s with proper logs (UART log/drive log/Traces).Collaborate with driver team/software team to trace out the failures.Project Name: Post silicon Validation on different form factors & sizes of PCIe based SSDs.
Roles & Responsibilities:
Need to go through product architecture and product related specs and need to develop test plan.Take the code from legacy internal product if any changes required modify accordingly and for new feature develop the test casesIdentify feature of NVMe to be validated and interacted actively with architect to freeze the list of features to be validated.Trigger all OEM specific test cases with the help of automation Tool.Debug the failures if necessary, raise the Jira’s with proper logs (UART log/drive log/Traces).Collaborate with driver team/software team to trace out the failures. Daily sync up with third party controller team to fix the firmware issues.Needs to prepare the reports with the help of team to achieve the QS.
Project Name: Post Silicon Validation of Secure Digital Host Controller IP
Roles & Responsibilities:
Designed test plan according to the specifications and responsible features.Developed test cases with respect to system features.Actively interacted with the designer team and raised JIRA tickets on occurrence of issues.Developed the code as per the delta feature by understanding the legacy code. Strong at understanding of SD Host controller 3.0 specification.Prepared test plan and developed code in C for the following compliance features. Card Initialization and Identification,Host Initialization &Card Lock/Unlock
Timeline
Technical staff Engineer
Mirafra Technology Private Limited, Qualcomm
03.2021 - Current
Product Validation Engineer
Micron Technology Operations India LLP
08.2019 - 03.2021
M.Tech - Embedded Systems
Annamacharya Institute of Technology And Sciences
09.2016 - 08.2018
Post Silicon Validation Engineer
EmWare Technologies (INDIA) Pvt. Ltd
08.2014 - 09.2016
B. Tech - ECE
JNTUA
01.2010 - 01.2014
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