Shikha Prajapati

Seasoned professional with over 8 years of experience in Analog and Mixed-Signal Layout, specializing in high-performance integrated circuit design and validation. Adept at managing complex test-chip assemblies.

Proficient in Virtuoso and Calibre, I excel in managing complex projects while mentoring junior engineers. My innovative approach to power planning and signal integrity has consistently enhanced design efficiency and quality.

Optimizing design workflows to meet stringent performance requirements. Demonstrated expertise in IC design, with a strong focus on delivering precise and reliable results.

• presented paper on the Application Readiness Checker (ARC) at CadenceLIVE India 2025 in Bangalore
• Presented EMIR analysis and workflow to check quality of IPS of NVM using Totem and Spres on Layoutology forum among ST employees

Stmicroelectronics (2021-2025)

NVM Memories of Various Configuration 

• This project involved the design of various NVM Memories

* Design Modification in Charge pumps to support various current loads as per memory size

* Access Time improvement in sense amplifier 

* Design Modification of Regulator block for various current loads as per memory size. 

* Design of Ring oscillator, Comparator at lower supply.

* Block level LVS and DRC fixes

BGR Thermal Decoding(C090D)   

 • This block is used to generate a voltage of 1.2V which is PVT independent. The circuit also generates multiple reference currents needed for other blocks.

* Floor plan of the entire block.

* Maintained the matching of Pref module, CTAT, PTAT Blocks. 

* Maintained the matching of resistor, differential pair, avoided crosstalk, reduced parasitics.

* Block level LVS and DRC fixes

Ambient Scientific (2017-2021)

Analog Multiply Accumulator (AMAC) (TSMC 40nm)(TSMC 12nm) 

• The block contains AMAC units which were used for performing MAC operation during AI inference.

*Design of all the Digital blocks used in the Analog Multiplier.

*Layout of the comparator which involved Calibration functionality.

*Layout of the Binary weighted DAC based on DigAn.

*Block level LVS and DRC fixes

Delta Sigma ADC (TSMC 40nm) 

• This project involved the design of a 3rd order Delta Sigma modulator targeting an SNR of more than 100db.

* Design of fully differential Op-amp block used in integratorsChallenges involved reducing Capacitive mismatches, WPE, Deep N-well for reducing noise. . 

* Isolation of analog components and Digital blocks . 

* Optimization was done based on extraction results. 

* Block level LVS and DRC fixes

Band Gap Reference (TSMC 40nm)         

• This block is used to generate a voltage of 1.2V which is PVT independent. The circuit also generates multiple reference currents needed for other blocks.

* Designed the layout of op-amp, bias circuit and trimming circuit. 

* Maintained the matching of resistor, differential pair, avoided crosstalk, reduced parasitics 

* Block level LVS and DRC fixes

SAR ADC (TSMC 40nm)   

• This project involved the design of a 14bit SAR ADC targeting an SNR of more than 75db.

* Floor plan of the entire block. 

* Layout of the Capacitive DAC and Resistive DAC. 

* Comparator Layout.

* DRC, LVS, ERC. SRAM (TSMC 40nm) 2017

* Floor Planning of Top Level , Row Decoder, Column Decoder and Peripherals layout

* Differential based Sense Amp layout

* Top Level Integration