Veera Kumar jalumuri
Bangalore
Summary
IMMEDIATELY AVAILABLE Candidate with 7.8 years of experience in Characterization , Quality analysis and methodology for SRAM memories ,standard cells and Analog macros . Looking for job change in Characterization & automation/ STA domain
Overview
8
8
years of professional experience
Work History
SOC Logic Design Engineer
Intel Corporation
Bangalore
01.2024 - Current
- Developed python automation to perform liberty OCV checks on standard cells
- Worked on place and route to validate standard cell libraries using fusion compiler
- worked on primetime tool to validate standard cell libraries using integration testcase.
- Resolved customer complaints in a timely manner.
- Participated in team meetings to discuss project progress updates.
Memory Characterization and CAD Engineer
Qualcomm India PVT limited
Bangalore
01.2022 - 01.2024
- worked on memory characterization on N3E custom memories and delivered libs with no quality issues
- worked on TSMC N3E and Samsung 4nm Technologies
- Generated CDL , GDS, DPF, SPF and DPF , APL sim2iprof, decap , inrush decap views
- Performed stimulus creation and simulations and created the .lib file generation across the PVT corners
- Conducted quality analysis on .lib files and worked on pin cap validation and delay validation methodologies
- POC for enabling CRON summary across active characterization .
- Mentored new CWF and model engineers on char flow
- acted as release POCV for 3months and ensured timely releases
- developed tcl based automation to calculate bank delay and another script to verify state of output pins from fsdb file.
- Created perl and python automation scripts to catch QA issues.
- worked on APL compiler development and has developed QA scripts
Memory Design Engineer
Sevitech Systems Pvt Ltd( Client Qualcomm)
Bangalore
04.2019 - 01.2022
- Worked on TSMC 22ull, 4nm and samsung 8nm , 5nm technologies
- Worked on memory characterization on 22ull pseudo dual port SRAM compiler characterization
- worked on N4 pseudo dual port SRAM memory compiler characterization
- worked on samsung 5nm two port register file compiler characterization
- worked on samsung 5nm Low Power single port SRAM compiler characterization using liberate_mx tool
Analog IP Characterization
Eximius design india Pvt limited
Bangalore
08.2018 - 04.2019
- worked on analog SERDES IP characterization on 10nm technology using siliconsmart tool
Analog IP Characterization Engineer
Wipro Pvt Ltd
Bangalore
09.2016 - 08.2018
- Worked on SERDES IP block level characterization on TSMC 16nm technology
- worked on generating NLDM/CCS/ECSM libs for 16nm tech node
Education
Electronics And Communications Engineering
IIIT-NUZVID
NUZVID,ANDHRA PRADESH05-2016
Class 12th - Class 12th
IIIT-NUZVID
NUZVID,Andhra Pradesh05-2012
Skills
- memory characterization
- library characterization
- QA
- LVF
- NLDM
- Liberty File
- Siliconsmart
- Liberate_mx
- Python
- perl
- Primetime
- Verilog
- Design compiler
- library compiler
Languages
Telugu
First Language
English
Upper Intermediate (B2)
B2
Hindi
Intermediate (B1)
B1
Timeline
SOC Logic Design Engineer
Intel Corporation
01.2024 - Current
Memory Characterization and CAD Engineer
Qualcomm India PVT limited
01.2022 - 01.2024
Memory Design Engineer
Sevitech Systems Pvt Ltd( Client Qualcomm)
04.2019 - 01.2022
Analog IP Characterization
Eximius design india Pvt limited
08.2018 - 04.2019
Analog IP Characterization Engineer
Wipro Pvt Ltd
09.2016 - 08.2018
Electronics And Communications Engineering
IIIT-NUZVID
Class 12th - Class 12th
IIIT-NUZVID
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