YADUKRISHNAN K S

Result-driven Design Verification Engineer with over 3 years of experience in advancing verification methodologies in high-speed interfaces such as PCIe Gen6 and Ethernet. Proficient in System Verilog, UVM and Python. I have succesfully lead multiple projects that improved verification efficiency by 30%, ensuring high-quality deliverables in SoC designs. Adept at utilizing tools like Verdi and Github copilot to streamline debuggin processes and enhance productivity.

Ultra Ethernet Controller: 

• Verified CBFC (Credit-Based Flow Control) feature in Ultra Ethernet.
• Developed scheduler component for packet scheduling based on RTL backpressure signals.
• Enhanced scoreboard for end-to-end comparison of CC_Update messages.
• Verified CF Update message handling and backpressure behavior.
• Implemented VIP callbacks and developed coverage models.

Ethernet PCS 1.6T MC Verification:

• Worked on verification of Ethernet PCS responsible for encoding, decoding, scrambling, and lane alignment.
• Developed sequences for reset scenarios including hardware and software resets.
• Integrated VIP and utilized callbacks for feature verification.
• Implemented covergroups for multiple features to ensure functional and code coverage.

PCle Gen6 Retimer Verification:

• Verified Low Latency Mode (LLM) and compliance features.
• Developed end-to-end latency checker (with and without PHY).
• Implemented configurable logic for LLM enable/disable.
• Developed testcases for transmit margin and receiver preset validation.
• Owned regression and debug.

CXL-Based System Verification: 

• Developed ATB and DDR trace checkers.
• Verified DOE and VDM flows including ISR handling.
• Integrated passive VIPs. Performed end-to-end SRAM data integrity checks.