Aishwarya Sridhar

• Led multiple high impact Shift left methodology projects in the field of digital design & verification and analog mixed signals.
• Represented the team of 20 to discuss scope, requirements, milestones with clients and ensuring timely delivery of projects
• Worked on the German government funded innovation project to build RTL and formal property generator
• Integrated and supported several EDA tools like Xcelium, Questa, Questa Formal, JasperGold, Conformal LEC, Onespin, Verilator and etc
• Developed a standard verification regression flow that was used across BUs having more than 300 stakeholders
• Worked on formally verifying design blocks like registers, cache memory, bus, mac and etc for flagship IPs of Infineon
• Automated in-house QA process for 3rd party tools and reduced the manual efforts significantly from man weeks to minutes
• Acted as the organization ambassador for university relationship programmes and actively involved in mentoring students

Key Achievements:

• The paper 'Automated Generation of Interval Properties From Trace-Based Function Models' selected for DVCon US 2024.
• Published 'Formal Coverage: An Approach to Analyze Property Holes' in Osmosis 2022
• Published 'Effortless, Methodical and exhaustive register verification using what you already have' in DVCon India 2021
• "Engineer of the quarter" for 8 consecutive quarters
• Runners up in Infineon Hackathon