Overview
Work History
Education
Skills
Certification
PROJECTS
Accomplishments
Timeline
Generic

Devang Sharma

Noida

Overview

1
1
year of professional experience
1
1
Certification

Work History

Design Engineer Trainee

Cadence Design Systems
Noida
01.2025 - Current
  • A part of Cadence's soft IP team, working on UVM verification of CXL protocol's RTL design ready for development. Working on numerous debugs particularly related to CXL Registers & CXL IDE.
  • Also contributed in functional coverage of top-level CXL for IP release. By writing, mapping and sampling coverpoints. Also learned APB, CXS and AXI5 Protocols.

DV Trainee

PinE Training Academy
Noida
07.2024 - 12.2025
  • Learned Verilog, digital electronics, SV, UVM, and scripting. Worked on RTL design and verification projects, such as the RISC processor and SPI protocol.

Education

B.Tech - Electronics And Communications Engineering

Jaypee Institute of Information Technology
Noida, India
06-2025

Class 12th - Science(PCM)

Kothari International School
Noida, India
04-2020

Skills

  • Languages: Verilog, SV, UVM, C/C
  • Tools: Virtuoso, Vivado, SVN, Xcelium, VManager, Linux, Innovus, MATLAB
  • Concepts: Digital Electronics, CMOS VLSI Design, RTL Design, Verification,
  • Protocols: CXL Protocol, CXS Protocol, AXI5 Protocol, APB Protocol, SPI Protocol

Certification

  • RTL to GDSII ASIC Design Flow:Hands-on training in full and semi-custom ASIC design using Cadence tools suite from RTL to tapeout, including STA.
  • Digital IC Design: Gained deep practical understanding of transistors (MOSFET/BJT) and built optimized ICs from scratch using CMOS, pass transistor, and transmission gate logic.
  • Verilog for an FPGA Engineer: Designed FSMs, ALU and sequential circuits in Verilog synthesized and implemented them on Xilinx Zedboard using Vivado.

PROJECTS

UVM verification of the APB protocol

  • Verified an APB master DUT using two agents, one acting as an APB slave, receiving commands, and the other as an AXI slave, giving commands to our APB master.

Designed a five-stage pipelined RISC processor

  • A processor consisting of 21-Instruction set encoded and fed to the RISC Processor in the form of a 32-bit command.

Design & Verification of SPI Protocol

  • Designed an SPI Master & 2 SPI Slaves and verified them.

Implementation of 16-bit ALU on FPGA Board

  • Designed a 16-bit ALU using verilog, then synthesized, implemented and uploaded it on Xillinx Zedboard FPGA using Xillinx Vivado.

Designed a 14T Full Adder using dynamic CMOS logic on Cadence Virtuoso

  • This was an implementation of a research paper: "A high speed 14 transistor full adder cell using novel 4 transistor XOR/XNOR gates based on dynamic CMOS logic" built using minimum possible transistors but maximum performance.

Implemented a 1101 sequence detector from its RTL design to STA till Tapeout

  • Followed the RTL to GDS2 flow for the FSM. Starting with its RTL design through verilog to verification(Xcelium), then synthesis of the code(Genus)

Smart Parking Maintenance & Assistance System

  • Developed a robust IoT & ML-based Smart Parking maintenance system for housing societies and parking lots. Incorporated on-chip ML on Raspberri Pi 4 for surveillance and gatekeeping and RFID along with Realtime Database to ensure vehicles are parked at their respective spaces only.

Research paper Implementation project: Fine Air

  • Developed an IoT and ML-based system using an MQ2 sensor to monitor vehicle emissions. Real-time gas data is stored in Google’s Realtime Database and visualized on a website. A regression model predicts emissions for the next 3 days, triggering user alerts if limits are exceeded. Both users and authorities can access this data via the web portal.

Accomplishments

  • Won 3 Hardware Hackathons
  • Got seed-funding by my college for an ECE project
  • Tech ECE Head of IEEE SB JIIT

Timeline

Design Engineer Trainee

Cadence Design Systems
01.2025 - Current

DV Trainee

PinE Training Academy
07.2024 - 12.2025

B.Tech - Electronics And Communications Engineering

Jaypee Institute of Information Technology

Class 12th - Science(PCM)

Kothari International School
Devang Sharma