UVM verification of the APB protocol
Designed a five-stage pipelined RISC processor
Design & Verification of SPI Protocol
Implementation of 16-bit ALU on FPGA Board
Designed a 14T Full Adder using dynamic CMOS logic on Cadence Virtuoso
Implemented a 1101 sequence detector from its RTL design to STA till Tapeout
Smart Parking Maintenance & Assistance System
Research paper Implementation project: Fine Air