KOKILAVANI M
Chennai
Summary
Adept PHY RTL Design Engineer from MBIT Wireless Private Limited with close to 3 years of hands on experience in Verilog coding and ASIC design. Demonstrated prowess in digital design, low power design, CDC, linting and problem-solving, significantly contributing to project successes. Driven by a passion for continuous learning and successfully navigating change. Committed to collaborating effectively within a team to leverage my knowledge and skills for exceptional engineering outcomes.
Overview
2
2
years of professional experience
1
1
Certification
Work History
PHY RTL Design Engineer
MBIT Wireless Private Limited
Chennai
07.2022 - Current
- Working as a PHY Layer Development Engineer.
- Implemented a channel estimation algorithm in RTL to enhance the efficiency of downlink channel data decoding.
- Handled DL channel decoding blocks and FSM controllers.
- Involved in DSP software - RTL interface discussion and conclusion as a part of hardware software partitioning.
- Documented microarchitecture for handled blocks, and modem architecture for overall DL procedures.
- Collaborated with the Verification and Validation team for design verification and validation sign-off.
- Performed RTL linting, warning clearance, and CDC on 200+ paths to ensure design correctness and reliability.
- Resolved timing issues across modules by means of STA.
- Debugged issues in RTL during validation using a logic analyzer tool.
- Analyzed and devised strategies for implementing probe features in overall downlink procedures, taking into account the trade-offs between area and debugging efficiency.
- Accomplished almost 90% code coverage for all handled modules.
Education
Bachelor of Engineering - Electronics And Communications Engineering
Madras Institute of Technology
Chennai07-2022
Skills
- Verilog coding
- Digital design
- Linux
- Issue debugging
- ASIC design
- Timing budget
- Low power analysis
- FPGA design
- Synthesis
- Vivado
- Xilinx ISE
- Synopsys VCS
- MATLAB
Certification
- RTL to GDS flow - NPTEL
- Certificate of Internship - VERZEO
Languages
Tamil
First Language
English
Advanced (C1)
C1
Hindi
Intermediate (B1)
B1
Research paper publication
Downlink Performance Analysis of the 5G PD-NOMA System, IEEE Conference Paper, https://ieeexplore.ieee.org/document/9938331
Accomplishments
- Secured State 4th and District 3rd in SSLC
- Achieved Best Dance Performer, Female, in college culturals
- Runner-up in the zonal-level handball competition
Timeline
PHY RTL Design Engineer
MBIT Wireless Private Limited
07.2022 - Current
- RTL to GDS flow - NPTEL
- Certificate of Internship - VERZEO
Bachelor of Engineering - Electronics And Communications Engineering
Madras Institute of Technology
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