Nerella Manikanta

5 Years of experience in VLSI Front end design and verification. Responsible for Functional verification using system Verilog, UVM. Developed Verification Components Driver, Monitor, Scoreboard, Interface and integrating all components with DUT. Coding Sequence items by constraining random variables. Creating Functional Coverage Models. Driving Coverage Closure. Executing Regressions. Knowledge in protocols like UART, APB. Knowledge on Computer architecture and Multi core processors.

• Thor V3 Processor verification, 08/2023 - Present, Processor Verification - MIPS, This project verifies the processor which is used in modems. Responsible for debugging the regression failures. Responsible for migrating the test cases from V2 to V3. Responsible for writing functional coverage for MPU., UVM, Assembly, System Verilog
• MMG- RDMA 400G CONTROLLER, 01/2023 - 06/2023, IP level Verification, Next version of the MEV. Responsible for verification of Protocol Transmit(PTX). Migrating all the testcases from MEV to MMG. Running regressions in MMG. Debugging the new failures., UVM, System Verilog
• MEV- RDMA 200G CONTROLLER, 02/2020 - 12/2022, IP Level Verification, 24, System Verilog, The RDMA Protocol Engine (PE) adds Remote Direct Memory Access (RDMA) capabilities to the traditional LAN functionality found in standard NICs. RDMA is a networking performance optimization that enables servers to communicate across a network using high-performance, low latency, zero-copy DMA semantics. It is designed to reduce host CPU utilization, host memory bandwidth used for network traffic, and network latency when compared to traditional networking stacks such as sockets with TCP/IP. Responsible for verification of Protocol Transmit (PTX), TransmitWork Queue Manager(WTX) blocks. Developed testcases and sequences. Added checkers. Coverage closure of PTX block. Debugged regression failures. Verified error generation scenarios.
• Synchronous FIFO -(In House), 03/2019 - 10/2019, IP level Verification, Developed UVM components Driver, Monitor, Scoreboard, Agent and Environment from scratch. Developed sequences, Testcases., UVM, System Verilog
• APB Protocol - (In House), 03/2019 - 10/2019, IP level Verification, Developed UVM components Driver, Monitor, Scoreboard, Agent and Environment from scratch. Developed sequences, Testcases., UVM, System Verilog

• Father's Name: Satya Narayana Nerella
• Date of Birth: 07/04/1994